Floating Point Vector Processing on an FPGA
Floating Point Vector Processing on an FPGA
Floating Point Vector Processing on an FPGA
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Memory Hierarchy<br />
• Supports modified Harvard style memory<br />
architecture<br />
• Separate instructi<strong>on</strong> <strong>an</strong>d data memory in local <strong>on</strong>chip<br />
RAM<br />
• Unified main memory (in other <strong>on</strong>‐chip RAM)<br />
• Local <strong>on</strong> chip RAM reduces traffic <strong>on</strong> the system bus<br />
• Program <strong>an</strong>d data size are limited by local <strong>on</strong>‐chip<br />
RAM size<br />
– <str<strong>on</strong>g>Vector</str<strong>on</strong>g> code is more compact th<strong>an</strong> scalar code!
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