Floating Point Vector Processing on an FPGA
Floating Point Vector Processing on an FPGA
Floating Point Vector Processing on an FPGA
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References<br />
[1] C. Kozyrakis <strong>an</strong>d D. Patters<strong>on</strong>, “Overcoming the Limitati<strong>on</strong>s of<br />
C<strong>on</strong>venti<strong>on</strong>al <str<strong>on</strong>g>Vector</str<strong>on</strong>g> Processors”, In Proceedings of the 30th Internati<strong>on</strong>al<br />
Symposium <strong>on</strong> Computer Architecture, S<strong>an</strong> Diego, California, June<br />
2003, pp. 399–409.<br />
[2] K. As<strong>an</strong>ovic, J. Beck, B. Irissou, B. Kingsbury, <strong>an</strong>d N. Morg<strong>an</strong>, “The T0<br />
<str<strong>on</strong>g>Vector</str<strong>on</strong>g> Microprocessor,” Hot Chips, vol. 7, pp. 187–196, 1995.<br />
[3] P. Yi<strong>an</strong>nacouras, J. Gregory Steff<strong>an</strong>, <strong>an</strong>d J<strong>on</strong>ath<strong>an</strong> Rose, VESPA:<br />
Portable, Scalable, <strong>an</strong>d Flexible <strong>FPGA</strong>‐Based <str<strong>on</strong>g>Vector</str<strong>on</strong>g><br />
Processors, Internati<strong>on</strong>al C<strong>on</strong>ference <strong>on</strong> Compilers, Architecture <strong>an</strong>d<br />
Synthesis for Embedded Systems (CASES), October 2008, Atl<strong>an</strong>ta, GA.<br />
[4] . Yu, G. Lemieux, <strong>an</strong>d C. Eaglest<strong>on</strong>, "<str<strong>on</strong>g>Vector</str<strong>on</strong>g> <str<strong>on</strong>g>Processing</str<strong>on</strong>g> as a Soft‐core CPU<br />
Accelerator," ACM Internati<strong>on</strong>al Symposium <strong>on</strong> <strong>FPGA</strong>, 2008.