Concurrent Systems II - Bad Request - Trinity College Dublin

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Translation Look-Aside Buffer • Before walking the page tables to translate a virtual address to a physical address… ◾ … the MMU checks each entry in the TLB • If the virtual page number is found, the cached secondary PTE is used by the MMU to translate the address … ◾ … and there is no need to walk the page tables in memory • If a TLB match is not found … ◾ … The MMU walks the page tables and locates the required PTE • The least recently used (LRU) TLB entry is now replaced with the current virtual page number and the PTE from the secondary page table • What are the TLB implications of a context switch? 170 Trinity College Dublin © Mike Brady 2007–2009
Page fault handling Start Access page table O/S reads page from disk no Page in main memory? Memory full? no yes Page tables updated yes Update TLB Page tables updated page fault handler CPU generates physical address 171 Trinity College Dublin © Mike Brady 2007–2009
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Concurrent Systems II (CS3D4/CS3BA2
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POSIX Threads • POSIX Threads aka
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Six Separate Threads Master Thread
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Where… • ‘thread’ is the ID
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Hello World -- Creating Threads int
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Hello World -- Thread Function void
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Wilde/Stoker/Ubuntu h-3.1$ cc -lpth
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Interaction • No thread interacti
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Interactions & Dependencies • Int
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…to do Parallel Programming • H
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Hardware Main Memory Level 2 Cache
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Shared Memory Machine • Each proc
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Concurrent Program • A Concurrent
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Communication • A parallel progra
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1 - Flow Dependence S1: write to lo
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3 - Output Dependence S1: write to
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Dependence in Loops j k k i 1 2 j 5
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How can we transform it? • We can
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Issues: • The variable sum, as wr
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Summarising: • We could paralleli
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Example • Sample function: y = 0.
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Synchronisation • We’ve looked
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Shared Variable S: Thread 1 after T
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Mutual Exclusion in pthreads. • M
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Shared Variable S Protected by Mute
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Lock and Unlock Mutex • pthread_m
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} /********** Critical Section ****
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Problem Tutorial • The transpose
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Producers and Consumers • Essenti
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Condition Variables (2) • Dramati
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From Thread U’s POV (2) • If C
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From Thread U’s POV (4) • Acqui
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Thread S (2) • Acquire Mutex M
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Semaphores • Computer Semaphores
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Semaphore Consumer ◾Acquire Mutex
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Semaphores (3) • Useful for count
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Sample Solution for ∏ • Calcula
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unsigned long long clock_cycles() {
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The Challenge of Concurrency • Co
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Concurrent Execution • A concurre
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Notation Trivial Concurrent Program
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Trivial Concurrent Program p1: n
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Example — Jumping Frogs • A fro
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If the frogs can only move “forwa
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State Diagrams for Processes • A
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Book Reference Principles of concur
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Correctness • (Correctness in Seq
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Using State machines • We can des
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The Critical Section Problem (2)
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Observations & Implications • Rem
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Simplify Critical Section Problem i
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State Transitions r1,s1,1 r1: await
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Deadlock Free? • Deadlock Free: I
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Scorecard Mutual Exclusion Deadlock
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Attempt #2 Critical Section Problem
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Attempt #2 Fails… • Attempt 2 f
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Attempt #3 Critical Section Problem
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Attempt #3 Fails… • Attempt 3 f
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Attempt #4 loop forever Critical Se
Page 119 and 120: Attempt #4 Fails… • Attempt 3 f
Page 121 and 122: Attempt #5, derived from #4 Critica
Page 123 and 124: Verification of concurrent programs
Page 125 and 126: A quick overview of some mathematic
Page 127 and 128: A quick overview of some mathematic
Page 129 and 130: Proving correctness by induction
Page 131 and 132: A quick overview of some temporal l
Page 133 and 134: A quick overview of some temporal l
Page 135 and 136: Temporal logic at work • Consider
Page 137 and 138: Promela • Promela [Protocol/Proce
Page 139 and 140: Process (2) • A process type (pro
Page 141 and 142: SPIN Hello World Example SPIN = Sim
Page 143 and 144: Promela Variables (2) • Arrays
Page 145 and 146: Statements (2) • The skip stateme
Page 147 and 148: If Statement if :: (n % 2 != 0) ->
Page 149 and 150: Atomic Statement atomic { stat1; st
Page 151 and 152: Process Execution / Evaluation Sema
Page 153 and 154: The Closed World Assumption • The
Page 155 and 156: Process memory management • In a
Page 157 and 158: Virtual memory • Give each proces
Page 159 and 160: Virtual memory 0 0 process 1 2 32 0
Page 161 and 162: Memory management requirements and
Page 163 and 164: E.g. Virtual memory implementation
Page 165 and 166: Multi-level page tables Virtual add
Page 167 and 168: Typical process memory layout memor
Page 169: Translation look aside buffer • E
Page 173 and 174: Fetch policy • When should a page
Page 175 and 176: Page replacement policy • A page
Page 177 and 178: Page replacement policy • First-I
Page 179 and 180: Clock Algorithm 179 Trinity College
Page 181 and 182: Resident set management • Variabl
Page 183 and 184: Resident set management Local Repla
Page 185 and 186: Resident set management Δ Working
Page 187 and 188: Resident set management 187 Trinity
Page 189 and 190: Cleaning policy • Page buffering
Page 191 and 192: Load control • We can use a few d
Page 193 and 194: Process state transitions • Proce
Page 195 and 196: Preemptive and nonpreemptive schedu
Page 197 and 198: Scheduling algorithms • First-Com
Page 199 and 200: Scheduling algorithms • Shortest-
Page 201 and 202: Scheduling algorithms • Priority
Page 203 and 204: Scheduling algorithms • Round-Rob
Page 205 and 206: Example Process Arrival Time Next B
Page 207 and 208: Scheduling algorithms • Multi-lev
Page 209 and 210: Scheduling algorithms • Multi-lev
Page 211 and 212: Multi-processor scheduling • Flyn
Page 213 and 214: Layered file I/O (1) Application Di
Page 215 and 216: Disk access • Disks are slow ◾
Page 217 and 218: Disk scheduling • So, the order i
Page 219 and 220: Disk scheduling algorithms (2) •
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Concurrent Systems II - Bad Request - Trinity College Dublin

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