Concurrent Systems II - Bad Request - Trinity College Dublin

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Hardware Memory Cache CPU Bus … … … Cache CPU Multiple Processor 22 Trinity College Dublin © Mike Brady 2007–2009
Shared Memory Machine • Each processor has equal access to each main memory location – Uniform Memory Access (UMA). ◾Opposite: Non-Uniform Memory Access (NUMA) • Each processor may have its own cache, or may share caches with others. ◾May have problems with cache issues, e.g. consistency, line-sharing, etc. 23 Trinity College Dublin © Mike Brady 2007–2009
Page 1 and 2: Concurrent Systems II (CS3D4/CS3BA2
Page 3 and 4: POSIX Threads • POSIX Threads aka
Page 5 and 6: Six Separate Threads Master Thread
Page 7 and 8: Where… • ‘thread’ is the ID
Page 9 and 10: Hello World -- Creating Threads int
Page 11 and 12: Hello World -- Thread Function void
Page 13 and 14: Wilde/Stoker/Ubuntu h-3.1$ cc -lpth
Page 15 and 16: Interaction • No thread interacti
Page 17 and 18: Interactions & Dependencies • Int
Page 19 and 20: …to do Parallel Programming • H
Page 21: Hardware Main Memory Level 2 Cache
Page 25 and 26: Concurrent Program • A Concurrent
Page 27 and 28: Communication • A parallel progra
Page 29 and 30: 1 - Flow Dependence S1: write to lo
Page 31 and 32: 3 - Output Dependence S1: write to
Page 33 and 34: Dependence in Loops j k k i 1 2 j 5
Page 35 and 36: How can we transform it? • We can
Page 37 and 38: Issues: • The variable sum, as wr
Page 39 and 40: Summarising: • We could paralleli
Page 41 and 42: Example • Sample function: y = 0.
Page 43 and 44: Synchronisation • We’ve looked
Page 45 and 46: Shared Variable S: Thread 1 after T
Page 47 and 48: Mutual Exclusion in pthreads. • M
Page 49 and 50: Shared Variable S Protected by Mute
Page 51 and 52: Lock and Unlock Mutex • pthread_m
Page 53 and 54: } /********** Critical Section ****
Page 55 and 56: Problem Tutorial • The transpose
Page 57 and 58: Producers and Consumers • Essenti
Page 59 and 60: Condition Variables (2) • Dramati
Page 61 and 62: From Thread U’s POV (2) • If C
Page 63 and 64: From Thread U’s POV (4) • Acqui
Page 65 and 66: Thread S (2) • Acquire Mutex M
Page 67 and 68: Semaphores • Computer Semaphores
Page 69 and 70: Semaphore Consumer ◾Acquire Mutex
Page 71 and 72: Semaphores (3) • Useful for count
Page 73 and 74:
Sample Solution for ∏ • Calcula
Page 75 and 76:
unsigned long long clock_cycles() {
Page 77 and 78:
The Challenge of Concurrency • Co
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Concurrent Execution • A concurre
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Notation Trivial Concurrent Program
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Trivial Concurrent Program p1: n
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Example — Jumping Frogs • A fro
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If the frogs can only move “forwa
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State Diagrams for Processes • A
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Book Reference Principles of concur
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Correctness • (Correctness in Seq
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Using State machines • We can des
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The Critical Section Problem (2)
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Observations & Implications • Rem
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Simplify Critical Section Problem i
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State Transitions r1,s1,1 r1: await
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Deadlock Free? • Deadlock Free: I
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Scorecard Mutual Exclusion Deadlock
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Attempt #2 Critical Section Problem
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Attempt #2 Fails… • Attempt 2 f
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Attempt #3 Critical Section Problem
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Page 117 and 118:
Attempt #4 loop forever Critical Se
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Page 121 and 122:
Attempt #5, derived from #4 Critica
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Verification of concurrent programs
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A quick overview of some mathematic
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A quick overview of some mathematic
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Proving correctness by induction
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A quick overview of some temporal l
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A quick overview of some temporal l
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Temporal logic at work • Consider
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Promela • Promela [Protocol/Proce
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Process (2) • A process type (pro
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SPIN Hello World Example SPIN = Sim
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Promela Variables (2) • Arrays
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Statements (2) • The skip stateme
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If Statement if :: (n % 2 != 0) ->
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Atomic Statement atomic { stat1; st
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Process Execution / Evaluation Sema
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The Closed World Assumption • The
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Process memory management • In a
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Virtual memory • Give each proces
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Virtual memory 0 0 process 1 2 32 0
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Memory management requirements and
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E.g. Virtual memory implementation
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Multi-level page tables Virtual add
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Typical process memory layout memor
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Translation look aside buffer • E
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Page fault handling Start Access pa
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Fetch policy • When should a page
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Page replacement policy • A page
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Page replacement policy • First-I
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Clock Algorithm 179 Trinity College
Page 181 and 182:
Resident set management • Variabl
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Resident set management Local Repla
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Resident set management Δ Working
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Resident set management 187 Trinity
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Cleaning policy • Page buffering
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Load control • We can use a few d
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Process state transitions • Proce
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Preemptive and nonpreemptive schedu
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Scheduling algorithms • First-Com
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Scheduling algorithms • Shortest-
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Scheduling algorithms • Priority
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Scheduling algorithms • Round-Rob
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Example Process Arrival Time Next B
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Scheduling algorithms • Multi-lev
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Scheduling algorithms • Multi-lev
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Multi-processor scheduling • Flyn
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Layered file I/O (1) Application Di
Page 215 and 216:
Disk access • Disks are slow ◾
Page 217 and 218:
Disk scheduling • So, the order i
Page 219 and 220:
Disk scheduling algorithms (2) •
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Concurrent Systems II - Bad Request - Trinity College Dublin

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