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Receiver radio characteristics Measurement conditions: T = 20°C, Vdd = 3,3V Sensitivity at 0.1% BER for all packet types 1 Maximum received signal at 0.1% BER 1 C/I co-channel at 0.1% BER 1 Adjacent channel selectivity C/I F = F 0 + 1MHz 1,2,3 Adjacent channel selectivity C/I F = F 0 - 1MHz 1,2,3 Adjacent channel selectivity C/I F=F 0 + 2MHz 1,2,3 Adjacent channel selectivity C/I F = F 0 - 2MHz 1,2,3 Adjacent channel selectivity C/I F = F 0 + 3MHz 1,2,3 Adjacent channel selectivity C/I F = F 0 - 5MHz 1,2,3 Adjacent channel selectivity 1,2,3 C/I F = F Image Modulation Typ Bluetooth specification Π/4 DQPSK -87 ≤ -70 8DQPSK -79 ≤ -70 Π/4 DQPSK -7 ≥ -20 8DQPSK -7 ≥ -20 Π/4 DQPSK +11 ≤ 13 8DQPSK +19 ≤ 21 Π/4 DQPSK -8 ≤ 0 8DQPSK -2 ≤ 5 Π/4 DQPSK -8 ≤ 0 8DQPSK -2 ≤ 5 Π/4 DQPSK -35 ≤ -30 8DQPSK -35 ≤ -25 Π/4 DQPSK -23 ≤ -20 8DQPSK -19 ≤ -13 Π/4 DQPSK -43 ≤ -40 8DQPSK -40 ≤ -33 Π/4 DQPSK -43 ≤ -40 8DQPSK -38 ≤ -33 Π/4 DQPSK -17 ≤ -7 8DQPSK -11 ≤ 0 Unit dBm dB Table 13: Receiver radio characteristics at enhanced data rate and temperature 20°C Notes: Results shown are referenced to input of the RF balun 1 Measurements methods are in accordance with the EDR RF Test Specification v2.0.E.2 2 Up to five exceptions are allowed in EDR RF Test Specification v2.0.E.2. WT12 is guaranteed to meet the C/I performance as specified by the EDR RF Test Specification v2.0.E.2. 3 Measured at F0 = 2405MHz, 2441MHz, 2477MHz 15
3. WT12 PIN DESCRIPTION WT12 31 30 29 1 2 3 4 5 6 7 8 9 10 11 12 13 14 GND GND VDD PIO2 PIO3 NRTS RXD PCMO USB_D+ USB_D- NCTS PCMI PCMC PCMS GND RF GND GND NC TXD PIO5 MOSI MISO SCLK NCSB PIO4 PIO7 PIO6 RES VDD GND 28 27 26 25 24 23 22 21 20 19 18 17 16 15 GND (pins 1, 15, 29 and 31) Figure 3: WT12 connection diagram Connect GND pins to the ground plane of PCB. VDD (pins 2 and 16) 3.3 V supply voltage connection. WT12 has an internal decoupling capacitor and LC filter to block high frequency disturbances. Thus external filtering is usually not needed. It is however re<strong>com</strong>mended to leave an option for an external high Q 10pF decoupling capacitor in case EMC problems arise. RES (pin 17) The RESET pin is an active high reset and is internally filtered using the internal low frequency clock oscillator. A reset will be performed between 1.5 and 4.0ms following RESET being active. It is re<strong>com</strong>mended that RESET be applied for a period greater than 5ms. WT12 has an internal reset circuitry, which keeps reset pin active until supply voltage has reached stability in the start up. This ensures that supply for the flash memory inside the WT12 will reach stability before BC4 chip fetches instructions from it. Schematic of the reset circuitry is shown in figure 4. Rising supply voltage charges the capacitor, which will activate the reset of WT12. The capacitor discharges through 220 kΩ resistor, which eventually deactivates the reset. Time constant of the RC circuitry is set such that the supply voltage is safely stabilized before reset deactivates. Pull-up or pull-down resistor should not be connected to the reset pin to ensure proper star up of WT12. 16
Page 1 and 2: WT12 Data Sheet V e r s i o n 2 . 3
Page 3 and 4: Contents: 1. Block Diagram and Desc
Page 5 and 6: TERMS & ABBREVIATIONS Term or Abbre
Page 7 and 8: 1. BLOCK DIAGRAM AND DESCRIPTIONS F
Page 9 and 10: Since the details of some methods a
Page 11 and 12: Radio characteristics and general s
Page 13 and 14: 6. Measured at F0= 2441MHz. 7. Up t
Page 15: 2.2 Radio Characteristics - Enhance
Page 19 and 20: CMOS input with weak internal pull-
Page 21 and 22: has to be connected to UART_RX. UAR
Page 23 and 24: 4.2 USB Interface WT12 USB devices
Page 25 and 26: USB_D+ WT12 USB_D- USB_ON VBUS Volt
Page 27 and 28: 4.3 SPI Interface The synchronous s
Page 29 and 30: PCM_OUT WT12 PCM_IN PCM_CLK Up to 2
Page 31 and 32: PCM_SYNC PCM_CLK PCM_OUT 1 2 3 4 5
Page 33 and 34: Name Bit position Description - 0 S
Page 35 and 36: 6. SOFTWARE STACKS WT12 is supplied
Page 37 and 38: The firmware has been written again
Page 39 and 40: 6.3 RFCOMM Stack RFCOMM SDP L2CAP H
Page 41 and 42: main WRAP THOR firmware. The user i
Page 43 and 44: 7. ENHANCED DATA RATE EDR has been
Page 45 and 46: 8. LAYOUT AND SOLDERING CONSIDERATI
Page 47 and 48: • Routing should be done in the i
Page 49 and 50: Figure 30: WT12 foot print and dime
Page 51 and 52: Figure 33: Tape information 50
Page 53 and 54: 11.2 FCC Federal Communications Com
Page 55 and 56: 12. ROHS STATEMENT WITH A LIST OF B

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