M_TTCAN - User Manual - Bosch Semiconductors and Sensors

M_TTCAN Revision 3.0.2
2.3.30 Rx FIFO 1 Configuration (RXF1C)
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0x0B0 F1OM F1WM[6:0] res F1S[6:0]
RP-0 RP-0 R-0 RP-0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
F1SA[15:2]
res
RP-0 R-0
Table 31
R = Read, P = Protected write; -n = value after reset
Rx FIFO 1 Configuration (address 0x0B0)
Bit 31F1OM: FIFO 1 Operation Mode
FIFO 1 can be operated in blocking or in overwrite mode (see Section 3.4.2).
0= FIFO 1 blocking mode
1= FIFO 1 overwrite mode
Bit 30:24 F1WM[6:0]: Rx FIFO 1 Watermark
0= Watermark interrupt disabled
1-64= Level for Rx FIFO 1 watermark interrupt (IR.RF1W)
>64= Watermark interrupt disabled
Bit 22:16 F1S[6:0]: Rx FIFO 1 Size
0= No Rx FIFO 1
1-64= Number of Rx FIFO 1 elements
>64= Values greater than 64 are interpreted as 64
The Rx FIFO 1 elements are indexed from 0 to F1S -1
Bit 15:2 F1SA[15:2]: Rx FIFO 1 Start Address
Start address of Rx FIFO 1 in Message RAM (32-bit word address, see Figure 2).
2.3.31 Rx FIFO 1 Status (RXF1S)
Bits 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0x0B4 DMS[1:0] res RF1L F1F res F1PI[5:0]
R-0 R-0 R-0 R-0 R-0 R-0
Bits 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
res F1GI[5:0] res F1FL[6:0]
R-0 R-0 R-0 R-0
Table 32
R = Read; -n = value after reset
Rx FIFO 1 Status (address 0x0B4)
Bits 31:30 DMS[1:0]: Debug Message Status
00= Idle state, wait for reception of debug messages, DMA request is cleared
01= Debug message A received
10= Debug messages A, B received
11= Debug messages A, B, C received, DMA request is set
34 14.02.2013