Direct Digital Down/Up Conversion for RF Control of Accelerating ...

Direct Digital Down/Up Conversion
for RF Control of Accelerating Cavities
C. Hovater, T. Allison, R. Bachimanchi, J. Musson and T. Plawski
Introduction
As digital receiver technology has matured, direct digital down/up conversion for RF control
of accelerating and beam conditioning cavities is now practical above 100 MHz. The typical RF
transceiver utilizes a heterodyne scheme, generating an intermediate frequency (typically < 100
MHz) which is then processed by an ADC or generated by a DAC. The suggestion here is to
eliminate the heterodyne stage and go directly into the ADC or out of the DAC to the cavity
frequency. Accelerators with accelerating cavity frequencies between 100 MHz and 1 GHz,
especially ones that have multiple frequencies, are good candidates for this technology. Two In
particular, are the CEBAF RF Separator cavity operating at 499 MHz and the Argonne proposal
for the Facility for Rare Isotope Beams (FRIB) accelerator. The FRIB project has multiple cavity
frequencies (345, 172.5, 115, and 57.5 MHz) which would require multiple RF receivers. The
benefit of using DDC is the elimination of RF transceivers, reducing the cost and simplifying the
RF control design. An additional benefit is the elimination of drifts and maintenance issues
associated with the RF transceiver. This paper discusses the possibility of such systems.
Direct Digital Conversion: Down and Up
Direct down conversion (DDC) of analog to digital converters (ADC) has been around for
many years and is the basis for most modern LLRF systems. In these cases they employ an
intermediate frequency (IF) typically below 100 MHz. The reason for this is that above 100 MHz
the signal to noise ratio (S/N) for the ADC falls off due to the effect clock jitter has on the
conversion process. In accelerators, the S/N ratio determines the achievable cavity field control
performance. For light sources and electron nuclear physics accelerators where field control
better than 0.5 o and 0.1% is expected, direct conversion may not be acceptable for this reason. In
addition the technology to sample above 1 GHz is not practical for the reason given.
In the case of a DDC system, the ADC is sampled directly and typically at a quadrature (I and
Q) sub-harmonic of the RF frequency. Figure 1 shows a cartoon of a DDC system and a
heterodyne system. The simplest quadrature sampling method is four times the RF signal. That is
the sampling across the RF is 90 degrees apart. If a frequency to be sampled is 50 MHz then the
sampling frequency is 200 MHz. Most ADCs can’t sample at such a high rate but one can sample
at a sub harmonic frequency using the following rule (Quadrature Sampling rate)/(2n+1). In the
example above for n=2 the sampling rate would be 40 MHz. Using the signals quadrature
components allows the control system an efficient method to control cavity field without extra
hardware (extra RF components and ADC).
Similarly digital up conversion can be accomplished by sampling a digital to analog converter
(DAC) with a quadrature sub harmonic [1]. DAC’s have been used for digital frequency
synthesis for many years and are available with outputs up to 500 MHz. The process here is to

again clock the DAC at the quadrature sub-harmonic of the required frequency. The quadrature
components are updated at this rate and series of harmonics are generated. Using the same
example as above and clocking a DAC at 40 MHz will generate spectral lines at fs/4 = 10 MHz
and then every fs/4 x (2n+1) or 30, 50, 70 MHz and so on. In this case, the signal of interest is 50
MHz and by filtering out this frequency we have generated our signal. The same can be done at
higher frequencies up to the limit of the DAC.
Figure 1: Block diagram of a heterodyne receiver and a direct down conversion receiver.
Receiver Requirements
Receiver requirements are determined by the required field/resonance control and the dynamic
range needed for gradient control. Using the FRIB linac as an example the needed cavity phase
and amplitude control is 0.5 o and 0.5% to meet its beam performance requirements. From this we
can develop a receiver specification for S/N. This specification must be maintained across a
gradient dynamic range of 10 dB (e.g. 5 to 15 MV/m). In addition we will add some margin for
error and make the field control requirements 0.25 o and 0.25%, which effectively gives us a 6 dB
error margin beyond the requirement. Looking at amplitude first and using the amplitude
stability specification, the S/N will need to be 52 dB [20 log(0.0025)] across the amplitude
dynamic range. So at the bottom end of the dynamic range our ADC must have 62 dB S/N (52 +
10).
Using the existing CEBAF Energy Upgrade receiver and eliminating the analog down
conversion portion, we can estimate a noise floor and a noise figure at the input of the ADC.
Figure 2 shows the front end receiver for a DDC.

Figure 2: Direct Down Conversion Receiver
From the required S/N we can make some assumptions. Looking at the ADC input range (0 dBm
to 10 dBm) and the extremely low noise floor (~ -106 dBm), signal strength is not an issue.
Therefore given the background noise of a receiver can maintain an S/N of 52 dB over the
dynamic range, we will meet our field control requirement. This effectively falls upon the ADC.
The S/N of an ideal ADC is given by the following equation
S / N [6.02N 1.76] [1]
where N is the number of bits in the ADC. Using this equation the S/N ratio for 12, 14 and 16 bit
ADCs is 74, 85.76, and 98.08 dB respectively. In reality reaching much beyond 80 dB even for
16 bit ADC communication (> 10 MSPS) is difficult. The effective input noise starts to go
beyond a least significant bit (LSB), for ADCs above 14 bits. Therefore your effective number of
bits (ENOB) is less than ideal. More realistic S/N ratios for these ADCs would be 70, 74, and 78
dB. Other factors must be included into the calculation including linearity and clock jitter. For
the DDC clock jitter is the most serious issue. As the ADC input frequency is increased the S/N
decreases primarily because of clock jitter. This can be understood by looking at figure 3 [2].
The voltage variation because of the clock jitter is larger for higher frequencies. This manifests
itself in S/N degradation. Putting all these affects into a realistic S/N equation gives
2 2 1 2 2V
NOISErms
S / N 20log10 (
ot jrms
)
[2]
N N
3 2 2
2
2
Where o is the analog input frequency (2 f), t jrms is the combined jitter of the ADC and clock,
is the average differential nonlinearity (DNL) of the ADC in LSBs, V noiserms is the effective input
noise of the ADC in LSBs and N is the number of ADC bits.

S/N
Figure 3: Conversion error as a function of clock jitter and analog input frequency [2].
Figures 4, shows a 12 bit ADC’s S/N vs input frequency for different clock jitters. For the
ANL FRIB proposal the spoke cavity has the highest operating frequency at 345 MHz. If the
ADC can reach 62 dB S/N for this frequency then any lower frequency will be met. From figure
4 we see that at 345 MHz the S/N is approximately 63 dB for a clock jitter of 300 fs.
75
12 Bit ADC S/N vs Input Frequency
70
65
60
55
100 fs
200 fs
300 fs
50
1.00E+07 1.00E+08 1.00E+09
Frequency (Hz)
Figure 4: 12 Bit ADC, Analog Devices AD9627

In addition the receiver assumptions here are for full sampling bandwidth of the ADC. A non
trivial amount of S/N improvement will be had with processing gain in the logic. Using FRIB as
an example with the RF at 345 MHz. The clock frequency needs to be a multiple of 345MHz x
4/(2n+1). Using n = 7 gives an even the clock frequency of 92 MHz. After separating the signal
into I and Q the rate will be ½ this value or 46 MHz. Our control bandwidth is 100 kHz (i.e. the
bandwidth needed for the feedback to control the cavity microphonics). As a rule oversampling
will improve S/N by log(N 1/2 ), where N is the amount over sampling. In the case above, N would
be 46 MHz/100kHz or 460. Therefore the S/N could theoretically improve by 26 dB. Even if we
only improve the S/N by 10 dB, this puts the S/N an order of magnitude higher than required.
Determining the phase requirement for the receiver is more subtle. Our control specification is
0.25 o over gradient change of 10 dB. To map this into S/N space we need to resolve the
amplitude difference between two angles separated by 0.25 o . In the I (cos) and Q (sin) domain
the worst case is near a 45 degree point where I = Q. Converting to that domain (either sin or
cos) and taking the difference between 45.0 o and 45.25 o gives a S/N of 50.2 dB* needed to
resolve either I or Q. Adding our imposed 10 dB for dynamic range gives a S/N of 60.2 dB
needed for phase control. One may also ask what happens near 0 o or 90 o . In this case I or Q is
approximately one and the S/N needed to resolve the angle is approximately 47 dB. So it is
easier to resolve near these angles. Looking at the worst case in phase we can say that receiver
S/N specification is being driven by the amplitude requirement of 52 dB.
Transmitter Design
The requirements for the transmitter can be relaxed when in comparison to the receiver. The
reason being is that it is in the feed-forward path of the control loop and signal errors are small in
comparison to power amplifier contributions. As long as amplifier saturation and other nonlinearity
do not hinder the feedback loop it is a straight forward process to generate the RF drive
signal out of a single DAC.
RF Separator Resonance Control
The proposed 12 GeV CEBAF RF separator resonant control would need to control cavity
resonance to one degree. In this case we do not need to control on amplitude only phase so this
will set up our receiver S/N. The amplitude difference between 45 o and 46 o gives an S/N of 38
dB needed to resolve the angle. At 499 MHz the graph in figure 4 shows a 12 bit ADC S/N of 60
dB with 300 fs of jitter. In this case the angle would be used to activate a valve controlling the
water flow through the separator cavity
FRIB RF Control
The FRIB RF system must be able to handle a number of cavity frequencies. Table 1 shows the
Cavity frequencies, the ADC clock, and DAC clock for such a DDC system [3]. All RF
frequencies and clock frequencies can be generated from a master reference of 276 MHz. In a
traditional RF receiver this is a problem considering the number of different RF boards necessary
*20log[cos(45) – cos(45.25)] = -50.2 dB, this effectively converts the

to accommodate the all of the RF and Local Oscillator (LO) frequencies. The advantage here is
to make one board with similar ADC’s and DACs where the only difference is the band pass
filter (BPF) in front of the ADC or DAC. The digital self excited loop control process developed
for the CEBAF 12 GeV upgrade would then be used for cavity field control [4].
Table 1
Down
(2n+1)
Up
Cavity
conversion
RF (MHz)
ADC
Clock
(MHz)
conversion
n Clock Div DAC
Clock
(MHz)
Clock Div
Frequency
5 th
Harmonic
(MHz)
57.5 46 2 6 46 6 57.5
115 92 2 3 92 3 115
172.5 46 7 10 138 2 172.5
345 92 7 5 276 1 345
Prototype Test Results
Using an Altera Stratix FPGA evaluation board with a 12 bit Analog Devices ADC (AD9433)
we were able to resolve phase and amplitude variations at both 499 MHz and 345 MHz. The
evaluation board has dual channel 20 MHz DACs that we used to display the resulting I and Q
signals. An Agilent RF signal source was used to generate the RF signal and the modulation. In
each case phase and amplitude was modulated at 400 Hz, respectively, using a square wave.
Figure 5 shows a scope trace of one degree of phase modulation at 499 MHz as detected by the
ADC. The phase modulation is processed in the Altera Stratix FPGA and then output through the
two DACs. The clock frequency in this case was 79.84 MHz (where n = 12). Both the I and Q
are shown and the they are approximately equal or at modulo 45 o .
Figure 5: I and Q DDC result of ½ o phase modulation on a 499 MHz carrier frequency. Scale
5mV/div and 1 msec/div.
Similarly Figure 6 shows the result of 0.5% amplitude modulation on a 345 MHz carrier
frequency as detected by the ADC. The clock frequency in this case was 92 MHz (where n = 7).

Figure 6: I and Q DDC result of 0.5% amplitude modulation on a 345 MHz carrier frequency.
Scale 5mV/div and 1 msec/div.
Summary
We have presented a proposal for Direct RF Down conversion which eliminates a stage (RF
board) for both the RF Separator Resonance control and RF control for ANL/FRIB proposal. The
stumbling block for any DDC is the degradation in S/N as the RF frequency increases. For both
projects it has been shown that using available technology a system can be built that meets
requirements for resonance and field control using DDC. Eliminating a series of RF boards
where each would be slightly different, simplifies the RF system making it easier to maintain. In
addition for large scale installations (>20 systems) such as FRIB, the elimination of the RF frontend
could save the project upwards of $500,000, over the design and construction of the project.
References
[1] L. Doolittle, “Plan for a 50 MHz Analog Output Channel”,
http://recycle.lbl.gov/~ldoolitt/plan50MHz/
[2] R. Reeder et al,”Analog-to-Digital Converter Clock Optimization: A Test Engineering
Perspective”, Analog Dialogue Volume 42 Number 1
[3] Conversations with Jean Delayen.
[4] C. Hovater, et al. “A Digital Self Excited Loop for Accelerating Cavity Field Control”,
Proceedings of the 2007 Particle Accelerator Conference, Albuquerque, NM