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simulation of a superheterodyne receiver using pspice - School of ...

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Block 7 – AM detector: as previously stated the resistor in the audio CR filter is set at<br />

100k as to increase the capacitor value to avoid stray capacitance. The capacitor at the<br />

input is reduced to 1nF, which is acceptable as the max value is11.73nF.<br />

Loading effects: the main problem associated with the hierarchy structure is the<br />

loading effects between the hierarchy blocks. It is essential to isolate the blocks from<br />

each other to avoid one block loading down the entire circuit and effectively stopping<br />

the <strong>receiver</strong> from working. The solution in Pspice is through transformers. Setting the<br />

inductor values in the transformer to L1=20uH and L2=0.3uH and a coupling <strong>of</strong><br />

0.9999 (i.e. practically 1) a step down transformer is achieved.<br />

As can be seen from Figs. 37-44 above transformers are placed in the following<br />

places:<br />

(1) A step down transformer is placed at the input <strong>of</strong> the RF amplifier (see<br />

Fig. 38) to avoid the 20k resistor from the AM generator being in parallel<br />

with the input resistance <strong>of</strong> the RF amplifier.<br />

(2) Another transformer is placed at the RF output (see Fig. 38) to avoid<br />

loading with the mixer. For convenience and design reasons this<br />

transformer is placed here and not at the input <strong>of</strong> the mixer because it<br />

incorporates the inductor from the tuned LC circuit in the RF load.<br />

(3) A transformer is used to couple the LO signal into the mixer (see Fig. 39).<br />

(4) The input <strong>of</strong> the first IF stage has a transformer (see Fig. 41) to avoid<br />

loading between the tuned LC circuit in the mixer load and input resistance<br />

<strong>of</strong> the IF amplifier.<br />

(5) The IF amplifier is a double tuned circuit and hence has two inductors in<br />

the load. Therefore these can be implemented as a transformer also to<br />

avoid loading effects between the two IF stages (see Fig. 41).<br />

40

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