36~chapter 04 atpg.pdf

f/1, a/0,a/1, c/1}
(d) The set of faults that are untestable when b=1 is
{b/1, c/1, d/1}
(e) The set of untestable faults based on the stem analysis of b is the
intersection of the (c) and (d), which is {c/1, d/1}
4.18 (PODEM)
(a) c/0: The first objective is c=1, which backtraces to b=1. Next, to
propagate the fault, the objective is a=1. At this time the D-frontier
is {g}. The next objective is f=0. With simulation, the fault is detected.
So the vector is abf=110.
(b) c/1: The first objective is c=0, which backtraces to b=0. Next, to
propagate the fault, a=1. At this time the D-frontier is g. The next
objective is f=0. With fault simulation we obtain that the fault is blocked.
So we backtrack to f=1. This also blocks the fault. So we revert f=X and
backtrack to a=0. This also blocks the fault. Finally we backtrack to b=1.
This cannot excite the fault. We are now at the root of the decision tree.
No more backtracks are possible. Thus the fault is untestable.
(c) d/0: The first objective is d=1, which backtraces to b=1. With
simulation we obtain the D-frontier to be {z}. The next objective is g=1.
Backtracing through an X-path leads us to f=0. Simulating at this time,
the D-frontier is still the same. The previous objective g=1 is not yet
justified. So we backtrace from g=1 again via an X-path. This time it takes
us to a=1. With simulation the fault is detected. So the vector is abf=110.
(d) d/1: The first objective is d=0, which backtraces to b=0. At this time
the D-frontier is empty since g=0. So we backtrack to b=1. But this cannot
excite the fault. Thus we backtrack again. No backtracks are possible,
thus the fault is untestable.
4.21 (Untestable Fault Identification)
If a fault f is combinationally untestable, then there exists no input
(PPI, PI) that can excite it and propagate it to any of PPO or PO. This
means that it is impossible in the sequential circuit that can take the
circuit to a state ∈ PPI with any PI that can excite f and propagate its
fault effects to either primary outputs or to the next-state flip-flops.
Thus, f is also sequentially untestable.
4.22 (FAN)
VLSI Test Principles and Architectures Ch. 4 – Test Generation – P. 6/8