36~chapter 04 atpg.pdf

Chapter 4 Exercise Solutions
4.1 (Random Test Generation)
We would enumerate the pseudo-exhaustive vectors for each of the three
primary output. Let T1 be the exhaustive test set of 8 vectors for inputs
a, b, c for output x, the other 4 primary inputs can take on random values.
Likewise, T2 is the test set of 16 vectors for inputs c, d, e, f for primary
output y, where the remaining 3 primary inputs take random values.
Finally, T3 is the test set of 8 vectors for the last primary output z.
The union of T1, T2, and T3 forms the pseudo-exhaustive test set.
This is not the minimal pseudo-exhaustive test set, since there are some
repeated vectors in T1, T2, and T3.
4.2 (Random Test Generation)
Recall that the detection probability is
d
T
f
f
= n , where f
T is the set
2
of vectors that can detect fault f, and n is the number of inputs in the
circuit. In this circuit, we have 3 inputs, so there is a total of 8
possible vectors.
(a) For e/0, two vectors, abc = {011, 111} can detect it. Thus
d
f
= 0.25
(b) For e/1, one vector, abc = 010 can detect it. Thus
d
f
= 0.125
(c) For c/0, two vectors, abc = {011, 101} can detect it, Thus
d
f
= 0.25
4.3 (Boolean Difference)
ence)
(a) The set of vectors that can detect e/0 is
VLSI Test Principles and Architectures Ch. 4 – Test Generation – P. 1/8

z
( e = 1) ⋅ = e ⋅ ( z ⋅ ( e = 0) ⊕ z( e = 1)
)
= e ⋅
= e ⋅
= e ⋅
d
d
( g ⊕ ( g + b)
)
g ⋅ g m b + g ⋅ ( g + b)
= e ⋅ g ⋅ b
e
( )
= e ⋅ ac ⋅b
( a + c)
⋅b
= bc + abc
= bc
Thus, the set of vectors is {011, 111}.
(b) The set of vectors that can detect e/1 is
z
( e = 0) ⋅ = e ⋅ ( z ⋅ ( e = 0) ⊕ z( e = 1)
)
= e ⋅
= e ⋅
= e ⋅
d
d
( g ⊕ ( g + b)
)
g ⋅ g m b + g ⋅ ( g + b)
= e ⋅ g ⋅ b
( )
= e ⋅ ac ⋅b
e
( a + c)
= bce + abe
⋅b
= abe
= abc
Thus, the set of vectors is {010}.
(c) The set of vectors that can detect c/0 is
d
z
( c = 1) ⋅ = e ⋅ ( z ⋅ ( c = 0) ⊕ z( c = 1)
)
dc
= c ⋅ a ⊕ b
= c ⋅
( )
( a ⋅b
+ a ⋅ b)
= abc + abc
Thus, the set of vectors is {011, 101}.
4.4 (Boolean Difference)
(a) The set of vectors that can detect a/1 is
VLSI Test Principles and Architectures Ch. 4 – Test Generation – P. 2/8

i
( a = 0) ⋅ = a ⋅ ( i ⋅ ( a = 0) ⊕ i( a = 1)
)
= a ⋅
= ab
d
da
( 0 ⊕ b)
Thus, the set of vectors is {01}.
(b) The set of vectors that can detect d/1 is
di
( d = 0) ⋅ = d ⋅ ( i ⋅ ( d = 0) ⊕ i( d = 1)
)
dd
= d ⋅
= d ⋅ ab
( 0 ⊕ ab)
But it is impossible to set a=1 and d=0 simultaneously. Thus, the set
of vectors is ∅ .
(c) The set of vectors that can detect g/1 is
i
( g = 0) ⋅ = g ⋅ ( i ⋅ ( g = 0) ⊕ i( g = 1)
)
= g ⋅
= g ⋅ ab
= ab ⋅ ab
= 0
d
dg
( 0 ⊕ ab)
Thus, the set of vectors is ∅ .
4.6 (Boolean Difference)
Since α and β are indistinguishable, any test t that detects one must
also detect the other. In other words, f ( t) f ( t)
α
≡
β
for any detection
vector t. On the other hand, if a vector v does not detect α , it must
also not detect β . In this case, f ( v) ≡ f ( v) ≡ f
α
β
, where f is the
fault-free circuit. Thus, for all vectors t, we have f ( t) f ( t)
Therefore, f ⊕ f = 0 .
4.7 (D Algorithm)
α
β
α
≡
β
.
VLSI Test Principles and Architectures Ch. 4 – Test Generation – P. 3/8

XNOR 0 1 D D X
0 1 0 D D X
1 0 1 D D X
D D D 1 0 X
D D D 0 1 X
x X X X X X
4.8 (D Algorithm)
Initially, we place a D on b. The D-frontier at this time includes {d,
e}. Next, we pick a D-frontier to propagate the fault effect across.
Suppose we pick d. Then, the decision a=0 is made. At this time, the
D-frontier becomes {x, e}. We pick the D-frontier that is closest to a
PO. Thus, we pick x. The next decision is e1=0. This decision implies y=1
and z=D. In other words, the fault-effect has been propagated all the way
to the PO. The J-frontier consists of {e1=0, b= D }. To justify e1=0, c=0
is sufficient. Justifying b= D is likewise straightforward, simply by
setting b=0. Thus the vector abc=000 detects the target fault b/1.
A similar decision process is made for the target fault e/0. However, in
this case, one would conclude that the fault is untestable.
4.9 (D Algorithm)
The valid value combinations for gate g include:
{Dxx, Dx1, D1x, D xx, D x1, D 1x, xDx, xD1, 1Dx, x D x, x D 1, 1 D x, xxD, x1D,
1xD, xx D , x1 D , 1x D }
4.10 (PODEM)
VLSI Test Principles and Architectures Ch. 4 – Test Generation – P. 4/8

First, we need to excite the fault. Since the fault is on a PI, the first
objective is b= D . Backtracing from the objective gives us b=0 as the first
decision. Logic simulating the current set of decisions made does not
change values of other gates. The D-frontier at this time includes {d,
e}. Next, we pick a D-frontier to attempt to propagate the fault effect
across. Suppose we pick d. Then, backtracing from the side input gives
us a=0 as the next decision. Logic simulating a=0 together with previous
decisions gives us a new D-frontier {x, e}. We pick the D-frontier that
is closest to a PO. Thus, we pick x. We again backtrace from the side input
e1=0 through an X-path. This leads us to c=0. Logic simulating c=0 with
earlier decisions gives us e=0, e1=0, e2=0, y=1, x=D, z=D. At this time
the fault has been detected. Thus the vector abc=000 detects the target
fault b/1.
A similar decision process is made for the target fault e/0. However, in
this case, one would conclude that the fault is untestable.
4.12 (Static Implications)
Since we know that f=1 implies x=1 and z=0, we can make {f=1, x=1, z=0}
as multiple objectives. Thus, any decisions selected should not violate
any of the objectives at any time. Likewise, we can use the implications
of z=0 to add to the multiple objectives.
4.13 (Static Implications)
(a) The implications for g=0 include
{a=0, b=1, c=1, d=0, e=0, f=1, g=0, h=0}
(b) The implications for $f=0$ include
{a=1, b=1, c=0, d=1, e=1, f=0, g=1, h=0}
4.15 (Dynamic Implications)
Since justifying e=1 via a=0 is not possible, it must be justified via
b=0. Thus, e=1 → b=0 is a dynamically learned implication.
4.17 (Untestable Fault Identification)
(a) The static logic implications of b=0 include
{b=0, c=0, d=0, e=1, g=0, z=0}
(b) The static logic implications of b=1 include
{b=1, c=1, d=1}
(c) The set of faults that are untestable when b=0 is
{b/0, c/0, d/0, e/1, g/0, z/0, a/0, a/1, f/0, f/1, d/1, g/1, e/0, f/0,
VLSI Test Principles and Architectures Ch. 4 – Test Generation – P. 5/8

f/1, a/0,a/1, c/1}
(d) The set of faults that are untestable when b=1 is
{b/1, c/1, d/1}
(e) The set of untestable faults based on the stem analysis of b is the
intersection of the (c) and (d), which is {c/1, d/1}
4.18 (PODEM)
(a) c/0: The first objective is c=1, which backtraces to b=1. Next, to
propagate the fault, the objective is a=1. At this time the D-frontier
is {g}. The next objective is f=0. With simulation, the fault is detected.
So the vector is abf=110.
(b) c/1: The first objective is c=0, which backtraces to b=0. Next, to
propagate the fault, a=1. At this time the D-frontier is g. The next
objective is f=0. With fault simulation we obtain that the fault is blocked.
So we backtrack to f=1. This also blocks the fault. So we revert f=X and
backtrack to a=0. This also blocks the fault. Finally we backtrack to b=1.
This cannot excite the fault. We are now at the root of the decision tree.
No more backtracks are possible. Thus the fault is untestable.
(c) d/0: The first objective is d=1, which backtraces to b=1. With
simulation we obtain the D-frontier to be {z}. The next objective is g=1.
Backtracing through an X-path leads us to f=0. Simulating at this time,
the D-frontier is still the same. The previous objective g=1 is not yet
justified. So we backtrace from g=1 again via an X-path. This time it takes
us to a=1. With simulation the fault is detected. So the vector is abf=110.
(d) d/1: The first objective is d=0, which backtraces to b=0. At this time
the D-frontier is empty since g=0. So we backtrack to b=1. But this cannot
excite the fault. Thus we backtrack again. No backtracks are possible,
thus the fault is untestable.
4.21 (Untestable Fault Identification)
If a fault f is combinationally untestable, then there exists no input
(PPI, PI) that can excite it and propagate it to any of PPO or PO. This
means that it is impossible in the sequential circuit that can take the
circuit to a state ∈ PPI with any PI that can excite f and propagate its
fault effects to either primary outputs or to the next-state flip-flops.
Thus, f is also sequentially untestable.
4.22 (FAN)
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Since both x and y are headlines, it suffices to backtrace to only these
points instead of primary inputs. Furthermore, since we know that y=1
→ x=0, when we backtrace to x, if the required value on x is 1, then
we can immediately backtrack in the decision process.
4.23 (Sequential ATPG)
(a) In time-frame 0, we propagate the D to output z, thus we need the
flip-flop value to be 1. In time-frame -1, the flip-flop value=1 can be
obtained by either the flip-flop value in time-frame -2 to be 1, or a=1.
However, since a=0 (the target fault), we must backtrace to the flip-flop
in time-frame -2. This will repeat indefinitely, resulting the fault to
be untestable using the 5-valued logic.
(b) In time-frame 0, we propagate the D to output z, thus we need the
flip-flop value to be 1/X in the 9-valued logic. In time-frame -1, the
flip-flop value=1/X can be obtained via either the flip-flop in time-frame
-2 or via a. In fact, a=1/0 (the target fault) suffices our need of a=1/X.
Thus, the vector sequence (a=1, a=X) is the test sequence.
4.24 (Sequential ATPG)
Yes, two faults a/0 and a/1 can be detected by the same test sequence.
Consider the test sequence v 0
, v 1
, ..., v k
, where v
k −1
excites a/0 and
propagates it to a state element, and v k
both propagates the fault-effect
from the flip-flop to a PO as well as excites and propagates the other
fault a/1 to a PO.
4.25 (Sequential ATPG)
The reachable states are {00, 01, 11}. The state diagram can be obtained
by constructing the truth table for the present-state and the PIs.
4.29 (Advanced Simulation-Based ATPG)
The sequence that is able to propagate a fault-effect from a flip-flop
FF
i
to a primary output for fault f 1
indicates that this propagation
sequence does not incidentally mask the fault f 1
along the way. This
propagation sequence will be ineffective for another fault
f j
if the
VLSI Test Principles and Architectures Ch. 4 – Test Generation – P. 7/8

fault-effect from
FF
i
is masked with the fault site for fault
f j
.
4.31 (Path-Delay ATPG)
(a) There are 14 paths in the circuit:
↑ afgj, ↓ afgj, ↑ bgj, ↓ bgj, ↑ befgj, ↓ befgj, ↑ cefgj, ↓ cefgj, ↑ chj,
↓ chj, ↑ dhj, ↓ dhj,↑ ij, ↓ ij.
(c) Both ↑ afgj and ↓ afgj are unsensitizable.
4.32 (Path-Delay ATPG)
Any path that requires a=1 and b=0 as a necessary condition would be
unsensitizable.
4.34 (Path-Del
Delay ATPG)
If the untestable path-delay fault is longer than the testable critical
path, then incidental detection could lead to yield loss.
4.36 (Bridging Faults)
The largest current is drawn from Vdd to Ground if the resistance between
them is minimal. So any test that can turn on parallel transisters at a
same time in both the AND and OR gates such that a conduction occurs from
Vdd to Ground would induce the largest current.
VLSI Test Principles and Architectures Ch. 4 – Test Generation – P. 8/8