Intel(r) 82552V Fast Ethernet PHY Datasheet
Intel(r) 82552V Fast Ethernet PHY Datasheet
Intel(r) 82552V Fast Ethernet PHY Datasheet
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<strong>82552V</strong> <strong>Fast</strong> <strong>Ethernet</strong> <strong>PHY</strong>—<strong>Datasheet</strong><br />
5.0 Initialization<br />
5.1 Power Up Sequence<br />
The <strong>82552V</strong> uses a 3.3 V power rail. The rail must meet the LCI power ramp<br />
requirements. The following flowchart shows the power up sequence for the <strong>82552V</strong>.<br />
Power up<br />
Internal power on circuit has<br />
detected valid power on input<br />
pins (3.3/1.0 volts)<br />
Internal Xosc stablizes<br />
Strapping are sampled<br />
Internal Power On Reset is deasserted<br />
<strong>82552V</strong> drives JRXD pins to ‘0’<br />
MAC activates JRSTSYNC<br />
reset<br />
<strong>82552V</strong> detects JRSTSYNC<br />
deassertion<br />
<strong>82552V</strong> drives a 5MHz<br />
clock on JCLK<br />
LCI interface initializes and<br />
becomes active<br />
<strong>PHY</strong> completes internal reset<br />
after JRSTSYNC deassertion<br />
and starts link auto-negotiation<br />
<strong>82552V</strong> MDIO registers are<br />
initialized by the MAC<br />
<strong>PHY</strong> establishes link<br />
Figure 4.<br />
Power Up Sequence Flowchart<br />
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