Intel(r) 82552V Fast Ethernet PHY Datasheet
Intel(r) 82552V Fast Ethernet PHY Datasheet
Intel(r) 82552V Fast Ethernet PHY Datasheet
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<strong>82552V</strong> <strong>Fast</strong> <strong>Ethernet</strong> <strong>PHY</strong>—<strong>Datasheet</strong><br />
Table 25. Receive error counter <strong>PHY</strong> register (Address Offset = 0x15, or 0d21)<br />
Mode<br />
RO<br />
15:0 Receive Error Count<br />
HW Rst<br />
0x0000<br />
Counter will peg at 0xFFFF and will not roll over.<br />
(when rx_dv is valid, count rx_er numbers)<br />
(in this version, only for 100Base-TX)<br />
SW Rst<br />
Retain<br />
Table 26. Virtual cable tester control <strong>PHY</strong> register (Address Offset = 0x16, or 0d22)<br />
Mode<br />
RO<br />
15:10 Reserved<br />
HW Rst Always 0<br />
Reserved.<br />
SW Rst Always 0<br />
9:8<br />
MDI Pair<br />
Select<br />
Mode<br />
HW Rst<br />
RW<br />
00<br />
Virtual Cable Tester Control registers. Use the Virtual Cable<br />
Tester Control Registers to select which MDI pair is shown in<br />
the Virtual Cable Tester Status register.<br />
00 = MDI[0] pair<br />
SW Rst Retain<br />
01 = MDI[1] pair<br />
10 = Reserved<br />
11 = Reserved<br />
7:1 Reserved h/s w 0 Always 0<br />
0 Enable Test<br />
Mode<br />
HW Rst<br />
RW<br />
0<br />
When set, hardware automatically disables this bit when VCT<br />
is done.<br />
1 = Enable VCT Test<br />
0 = Disable VCT Test<br />
SW Rst Retain<br />
Table 27. LED control <strong>PHY</strong> register (Address Offset = 0x18, or 0d24)<br />
Bits Symbol Type Description<br />
15 Disable LED<br />
14:12 Led on time<br />
Mode<br />
R/W<br />
HW Rst 0<br />
SW Rst<br />
Retain<br />
0 = Enable<br />
1 = Disable<br />
Mode<br />
HW Rst<br />
R/W<br />
100<br />
001 = 10ms<br />
010 = 21 ms<br />
011 = 42ms<br />
SW Rst Retain<br />
100 = 84 ms<br />
101 = 168ms<br />
110 to 111 = 42ms<br />
41
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