Intel(r) 82552V Fast Ethernet PHY Datasheet
Intel(r) 82552V Fast Ethernet PHY Datasheet
Intel(r) 82552V Fast Ethernet PHY Datasheet
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<strong>82552V</strong> <strong>Fast</strong> <strong>Ethernet</strong> <strong>PHY</strong>—<strong>Datasheet</strong><br />
10 Reserved h/s w 0 Always 0<br />
9:8 Energy Detect<br />
6:5<br />
MDI Crossover<br />
Mode<br />
Mode<br />
R/W<br />
HW Rst 0<br />
SW Rst<br />
Retain<br />
0x = Off<br />
10 = Sense only on Receive (Energy Detect)<br />
11 = Sense and periodically transmit NLP<br />
Mode R/W Changes to these bits are disruptive to the normal operation;<br />
therefore any changes to these registers must be followed by<br />
a software reset to take effect.<br />
HW Rst 11 00 = Manual MDI configuration<br />
SW Rst Update<br />
01 = Manual MDIX configuration<br />
10 = Reserved<br />
11 = Enable automatic crossover for all modes<br />
4:3 Reserved h/s w 0 Always 0<br />
2 SQE Test<br />
Mode<br />
R/W<br />
HW Rst 0<br />
SW Rst<br />
Retain<br />
SQE Test is automatically disabled in full-duplex mode<br />
regardless<br />
of the state of register 16.2<br />
1 = SQE test enabled<br />
0 = SQE test disabled<br />
1 Polarity Reversal<br />
Mode<br />
HW Rst<br />
R/W<br />
0<br />
If polarity is disabled, then the polarity is forced to be normal<br />
in<br />
10BASE-T.<br />
SW Rst Retain<br />
1 = Polarity Reversal Disabled<br />
0 = Polarity Reversal Enabled<br />
Mode<br />
R/W<br />
0<br />
Disable<br />
Jabber<br />
HW Rst 0<br />
Jabber has effect only in 10BASE-T half-duplex mode.<br />
1 = Disable jabber function<br />
0 = Enable jabber function<br />
SW Rst<br />
Retain<br />
Table 21. <strong>PHY</strong> specific status <strong>PHY</strong> register (Address Offset = 0x11, or 0d17)<br />
Bits Symbol Type Description<br />
15:14 Speed<br />
13 Duplex<br />
Mode<br />
HW Rst<br />
RO<br />
00<br />
These status bits are valid only after resolved bit 17.11 = 1.<br />
The resolved bit is set when Auto-Negotiation is completed or<br />
Auto-Negotiation is disabled.<br />
SW Rst Retain<br />
11 = Reserved<br />
10 = Reserved<br />
01 = 100 Mbps<br />
00 = 10 Mbps<br />
Mode<br />
HW Rst<br />
RO<br />
0<br />
This status bit is valid only after resolved bit 17.11 = 1. The<br />
resolved bit is set when Auto-Negotiation is completed or Auto-<br />
Negotiation is disabled.<br />
SW Rst Retain<br />
1 = Full-duplex<br />
0 = Half-duplex<br />
Mode<br />
RO<br />
12<br />
Page Received<br />
(real-time)<br />
HW Rst 0<br />
1 = Page received<br />
0 = Page not received<br />
SW Rst<br />
Retain<br />
35
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