Intel(r) 82552V Fast Ethernet PHY Datasheet

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82552V Fast Ethernet PHY—Datasheet Mode R/W 3:0 reserved HW Rst 4’hE SW Rst Retain Table 33. System mode control 3 (Address Offset = 0x03 (Hex), or 3(Decimal)) Mode R/W 15 Reserved HW Rst 0 SW Rst 0 14 First_LUFrame_TX 13 Phy_pll_on Mode R/W HW Rst 0 SW Rst Retain Mode R/W HW Rst 1 SW Rst Retain 1 = the frame with link_status(register17.10) asserted in the middle of the frame will not be transmitted at all; 0 = frames will be transmitted when link is up. PLL control bit, makes AND connection with input pin phy_pll_on to control PLL, 1 = PLL is always on, except iddq mode; 0 = PLL is control by hibernate module. Mode R/W 12:11 reesrved HW Rst 2’b11 SW Rst Retain 10 LED test control Mode R/W HW Rst 0 SW Rst Retain 1: when power on reset, the LED will not light. 0: when power on reset, the LED will light for 2.5s. 9:0 reserved Mode HW Rst SW Rst R/W 10’h3FF Retain 45
Datasheet—82552V Fast Ethernet PHY Table 34. Hibernation Mode Control Register (Address Offset = 0x0b (Hex), or 11 (Decimal)) 15 Ps_hib_en 14 Wake_mode Mode R/W HW Rst 1 SW Rst retain Mode R/W HW Rst 0 SW Rst retain Power hibernate control bit; 1: hibernate enable 0: hibernate disable 1:PHY wake up by energy detect or wake up pin 0:PHY wake up only by energy detect Mode R/W 13 reserved HW Rst 1 SW Rst retain 12 Hib_pulse_sw 11 Gate_25m_en_sw Mode R/W HW Rst 1 SW Rst retain Mode R/W HW Rst 1 SW Rst retain 1: when hibernate, PHY sends NLP pulse and detects signal from cable. 0: when hibernate, PHY doesn’t send NLP pulse and only detects signal from cable. 1:when hibernate, shut off 25m clock of autonegotiation 0:25m clock to auto-negotiation is not controlled by hibernate Mode R/W 10:0 reserved HW Rst 11’h400 SW Rst retain Table 35. 100BASE-TX Test Mode Register (Address Offset = 0x10 (Hex), or 16 (Decimal)) Mode R/W 15 TM100_ENA HW Rst 0 Enable 100BASE-TX loopback test mode. SW Rst Mode Retain R/W 14:8 Reversed HW Rst 7’h00 Always 0. SW Rst 0 46
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Intel(r) 82552V Fast Ethernet PHY Datasheet

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