Intel(r) 82552V Fast Ethernet PHY Datasheet
Intel(r) 82552V Fast Ethernet PHY Datasheet
Intel(r) 82552V Fast Ethernet PHY Datasheet
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<strong>82552V</strong> <strong>Fast</strong> <strong>Ethernet</strong> <strong>PHY</strong>—<strong>Datasheet</strong><br />
Table 17.<br />
Auto-Negotiation Advertisement <strong>PHY</strong> Register (Address Offset = 0x04, or<br />
0d04)<br />
Bits Symbol Type Description<br />
Mode<br />
R/W<br />
15 Reserved<br />
HW Rst 0<br />
Reserved<br />
SW Rst<br />
Mode<br />
Update<br />
RO<br />
14 Ack<br />
HW Rst Always 0<br />
SW Rst Always 0<br />
Must be 0<br />
Mode<br />
R/W<br />
13 Remote Fault<br />
HW Rst 0<br />
SW Rst Update<br />
Mode RO<br />
1 = Set Remote Fault bit<br />
0 = Do not set Remote Fault bit<br />
12 Reserved<br />
HW Rst Always 0<br />
Always 0.<br />
SW Rst Always 0<br />
11 Asymmetric Pause<br />
10 PAUSE<br />
Mode<br />
HW Rst<br />
R/W<br />
1<br />
The value of this bit will be updated immediately after writing<br />
this register. But the value written to this bit does not takes<br />
effect until any one of the following occurs:<br />
• Software reset is asserted (register 0.15)<br />
SW Rst Update<br />
• Restart Auto-Negotiation is asserted (register 0.9)<br />
• Power down (register 0.11) transitions from power down to<br />
normal operation<br />
• Link goes down<br />
1 = Asymmetric Pause<br />
0 = No asymmetric Pause<br />
(this bit has added the pad control and can be set from the<br />
F001 top, its default value is one)<br />
Mode<br />
HW Rst<br />
R/W<br />
1<br />
The value of this bit will be updated immediately after writing<br />
this register. But the value written to this bit does not takes<br />
effect until any one of the following occurs:<br />
• Software reset is asserted (register 0.15)<br />
SW Rst Update<br />
• Restart Auto-Negotiation is asserted (register 0.9)<br />
• Power down (register 0.11) transitions from power down to<br />
normal operation<br />
• Link goes down<br />
1 = MAC PAUSE implemented<br />
0 = MAC PAUSE not implemented<br />
(this bit has added the pad control and can be set from the<br />
F001 top, its default value is one)<br />
Mode<br />
RO<br />
9 100BASE-T4<br />
HW Rst Always 0<br />
Not able to perform 100BASE-T4<br />
SW Rst Always 0<br />
31
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