Intel(r) 82552V Fast Ethernet PHY Datasheet

82552V Fast Ethernet PHY—Datasheet
Table 13. Control PHY Register Descriptions (Address Offset = 0x00, or 0d00)
Bits Symbol Type Description
15 Reset
14 Loopback
13
Speed Selection
(LSB)
12 Auto-negotiation
Mode
HW Rst
R/W
0
PHY Software Reset. Writing a “1” to this bit causes the PHY to
be partially reset. This bit is cleared after Write operation. The
reset takes effect immediately after the bit is set.
SW Rst SC
1= PHY reset
0 =Normal operation
Mode
HW Rst
R/W
0
When loopback is activated, the transmitter data presented on
MII TXD is looped back to MII RXD internally. Link is broken
when loopback is enabled.
SW Rst 0
1 = Enable Loopback
0 = Disable Loopback
Mode R/W Upon hardware reset, this bit and 0.6 bit are determined by
anen (bit0.12) and speed_i (phycore interface pin):
HW Rst See Desc.
anen {0.6 , 0.13}
0 {1’b0, speed_i}
SW Rst
1 2’b01
(00:10Mbps; 01:100Mbps; 10,11:Reserved)
Mode R/W
This bit determined by ANEN_i (phycore interface pin) upon
HW Rst See Desc. hardware reset.
1 = Enable Auto-Negotiation Process
0 = Disable Auto-Negotiation Process
SW Rst
11 Power Down
10 Isolate
Mode
HW Rst
R/W
0
When PHY is switched from power down to normal operation,
software reset and Auto-Negotiation Restart are performed
even bit Reset (0.15) or bit Restart Auto-Negotiation (0.9) is
not set.
SW Rst 0
1 = Power down
0 = Normal operation
Mode
R/W
HW Rst 0
SW Rst 0
Not implemented.
(The GMII/MII/TBI output pins are tri-stated when this bit is set
to 1.
The GMII/MII/TBI inputs are ignored.
1 = Isolate
0 = Normal operation)
9
Restart Autonegotiation
Mode R/W,SC
HW Rst 0
SW Rst SC
Auto-Negotiation automatically restarts after hardware or
software reset regardless of whether or not the restart bit (0.9)
is set.
1 = Restart Auto-Negotiation Process
0 = Normal operation
8 Duplex Mode
Mode RW,SC Upon hardware reset , this bit depends on duplex_i (phycore
interface signal) and anen bit(0.12):
HW Rst
SW Rst
See
Desc.
0.12 0.8
0 0
1 duplex_i
1:Full Duplex
0 :Half Duplex
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