Digital Current Control of a Voltage Source Converter With Active ...

1364 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 21, NO. 5, SEPTEMBER 2006 

Digital Current Control of a Voltage Source Converter 

With Active Damping of LCL Resonance 

Eric Wu, Member, IEEE, and Peter W. Lehn, Senior Member, IEEE 

Abstract—Inductance–capacitor–inductance (LCL)-filters installed 

at converter outputs offer higher harmonic attenuation 

than L-filters, but careful design is required to damp LCL resonance, 

which can cause poorly damped oscillations and even 

instability. A new topology is presented for a discrete-time current 

controller which damps this resonance, combining deadbeat 

current control with optimal state-feedback pole assignment. By 

separating the state feedback gains into deadbeat and damping 

feedback loops, transient overcurrent protection is realizable while 

preserving the desired pole locations. Moreover, the controller is 

shown to be robust to parameter uncertainty in the grid inductance. 

Experimental tests verify that fast well-damped transient 

response and overcurrent protection is possible at low switching 

frequencies relative to the resonant frequency. 

Index Terms—Electromagnetic interference (EMI), inductance–capacitor–inductance 

(LCL)-filter, voltage source converters 

(VSCs). 

I. INTRODUCTION 

VOLTAGE source converters (VSCs) are commonly coupled 

to the grid through a simple L-filter. Alternatively, an 

inductance–capacitor–inductance (LCL)-filter may be installed 

at the converter output as shown in Fig. 1. The inductor 

and capacitor are locally installed, while inductor includes 

both locally installed and line inductance. The higher harmonic 

attenuation of this type of filter permits the use of a lower 

switching frequency to meet harmonic limits, increasing efficiency, 

reducing electromagnetic interference (EMI) and lowering 

overall costs [1]. 

However, the LCL-filter’s frequency response has a resonant 

peak which can be internally excited in the control loop if the 

controller is not suitably designed. External loads, disturbances, 

or transients can also excite the resonance, giving rise to poorly 

damped oscillations and in the worst case, instability. This resonance 

may be damped by the controller, a concept known as 

“active damping” [2]. 

In [2], a lead compensation scheme was used to achieve 

active damping for a -frame PI current controller. With 

twice-per-switching-period sampling, the controller was able 

to achieve high bandwidth with a relatively low switching 

Manuscript received May 31, 2005; revised December 8, 2005. This work was 

presented in part at APEC’05, Austin, TX, March 6–10, 2005. This work was 

supported by the Natural Sciences and Engineering Research Council of Canada 

(NSERC) and by the University of Toronto. Recommended by Associate Editor 

D. Maksimovic. 

The authors are with the Department of Electrical and Computer Engineering, 

University of Toronto, Toronto, ON M5S 3G4, Canada (e-mail: 

lehn@ecf.utoronto.ca). 

Digital Object Identifier 10.1109/TPEL.2006.880271 

Fig. 1. One-line diagram of the LCL system. 

frequency (relative to the filter resonant frequency), which 

was verified experimentally. Unfortunately, amplification of 

high-frequencies is a concern in lead compensation schemes. 

In [3], the authors applied capacitor current feedback to damp 

resonance in the LCL-filter, also achieving stable high bandwidth 

current control. However, the sampling and switching 

frequencies used were unspecified. In both [2] and [3], the 

modeling, design and analysis were done in the s-domain. The 

use of -domain analysis of the system ignores the inherent 

discrete nature of pulsewidth modulation (PWM) systems and 

digital controllers, and may not be accurate at low switching 

frequencies, where delays can be significant. 

In [4], a discrete-time approach was used, with cascaded 

loops to control grid current, capacitor voltage and converter 

current. However, capacitor voltage control is undesirable as 

it may require excessive converter current, to achieve voltage 

regulation, particularly if the grid interface inductance is 

small. The -plane root locus of the system also showed low 

stability margins, with one pole close to the unit circle. 

Reference [5] showed that the lead compensation used in [2] 

is applicable to a discrete-time controller. However, as in [2], 

lead compensation amplifies capacitor ripple as well as and 

sensor noise, limiting the amount of lead compensation that can 

be practically applied toward damping. 

Some literature relevant to the control of LCL-filtered 

converters can be found in the area of uninterruptible power 

supplies (UPS), which use a similar LC-filter. References [6] 

and [7] demonstrated the use of separate deadbeat current 

and voltage loops which guaranteed trajectory control of individual 

states. The deadbeat current loops of [6] and [7] can 

provide faster transient overcurrent protection than that of PI 

controllers. This concept has not yet been applied to the LCL 

topology. Another important work in this area is [8], which 

introduced the concept of a “virtual resistor” and showed that a 

proportional feedback was sufficient to damp LC resonance. 

This paper presents a new method of current control for LCLinterfaced 

grid-connected three-phase voltage source converters 

using a rigorous discrete-time model. The controller damps the 

LCL resonance, and can provide high-bandwidth performance 

0885-8993/$20.00 © 2006 IEEE

WU AND LEHN: DIGITAL CURRENT CONTROL OF A VOLTAGE SOURCE CONVERTER 1365 

at relatively low switching frequencies. This new system allows 

for the flexible, systematic design approach of pole assignment 

while retaining control of the current trajectory, providing transient 

overcurrent protection even when the controller’s overall 

performance criteria cannot be met [9]. 

II. SYSTEM MODELING 

Assuming that the impedances of the three-phase system of 

Fig. 1 are balanced, the differential equations governing the 

three-phase voltage and current vectors are 

The three-phase vectors , , , , and 

in (1)–(3) can be replaced by complex space vectors , , 

, , and in the form by applying 

the amplitude-invariant Clarke transformation 

(1) 

(2) 

(3) 

(4) 

Fig. 2. SPWM with twice-per-period sampling. 

The PWM pattern generator generates independent gating 

waveforms for each leg of the three-phase converter as shown 

in Fig. 2. 

With a symmetrical carrier, the desired average terminal 

voltage can be reached over half of a switching period , 

during which the voltage command is held and compared to the 

triangular carrier to calculate the duty cycle. Hence sampling 

occurs twice per switching period at frequency 1 .In 

order to accurately model the behavior of the PWM pattern generator 

and the digital controller, the differential equations are 

discretized by the zero-order hold method. The discrete-time 

state-space model is given by [10] 

and assuming no zero-sequence currents. 

The space-vectors may then be projected onto complex variables 

in the synchronously rotating -frame 

by performing the substitution 

on each 

space vector, with synchronous frequency . Assuming 

0, the complex -frame differential equations are then 

given by 

where 

(9) 

(5) 

(6) 

(7) 

The subscripts will henceforth be dropped for convenience. 

Equations (5)–(7) can be now written in state-space form as 

(8) 

where 

Due to finite computation time, the voltage command calculated 

during the present timestep must be requested by the controller 

during the next timestep. This behavior is modeled as a 

one-timestep delay between the converter voltage command 

and the terminal voltage 

(10) 

Considering as a state and as a new input, this delay may 

be incorporated into the model by rearranging the state equation 

[11]. The augmented state model is then given by 

(11) 

(12) 

where


Fig. 3. 

Proposed complex current controller. 

Fig. 4. Equivalent control diagram. 

This complex-valued discrete-time state model will be used in 

the control design and analysis which follows. 

III. CONTROL DESIGN 

The control design and analysis have been performed using 

the complex state model, eliminating the redundancy between 

d and axes and the need to explicitly decouple them. The 

proposed control structure is shown in Fig. 3. At its core is a 

deadbeat current controller, which provides transient overcurrent 

protection. The deadbeat current reference is the difference 

of the output of the integrator , which ensures zero 

steady-state error, and feedback current which incrementally 

modifies the reference to provide damping without controlling 

the capacitor voltage. 

A. Deadbeat Current Controller 

The deadbeat current controller is designed such that 

reaches its reference in a fixed, finite number of timesteps, 

without overshoot. Since the current trajectory is controlled, 

transient overcurrent protection can be guaranteed by placing a 

limiter on the deadbeat current reference as shown in Fig. 3. To 

determine the deadbeat gains , and , the state equation 

of (11) is rewritten symbolically 

If the sampling rate is fast enough such that the system voltage 

does not change rapidly over a single timestep, then it can 

be assumed that . Substituting and 

solving for gives the required converter command voltage 

where 

(16) 

(17) 

(18) 

(19) 

B. Damping and Integral Gain Calculation 

Damping of capacitor oscillations is achieved by state feedback 

through the gain , while zero steady-state error is guaranteed 

by the integral with gain . Calculation of these gains 

can be simplified by using the single-loop feedback control diagram 

in Fig. 4. Provided the current limiter does not engage, it 

can be shown that this diagram has the same closed-loop state 

response as Fig. 3 provided that 

(13) 

Due to the previously-mentioned one-timestep computation 

delay, the current can be made to reach its reference in a minimum 

of two timesteps. A control law can therefore be found 

which ensures that . The state equation for is 

(14) 

Incrementing by one timestep and substituting for , , 

, and from (13) yields 

(20) 

(21) 

It should be noted that control diagram of Fig. 4 is only equivalent 

to that of Fig. 3 when the current limiter is not engaged. 

If excessive current is requested, the converter has no current 

capacity to damp capacitor oscillations and the incremental 

damping gain, is effectively disabled. 

To determine and , the open-loop state model of (11) 

must first be augmented with the integrator state equation [10] 

(22) 

The final, augmented state model is 

(15) 

(23)


where 

Simple pole assignment may be used to determine the input 

Fig. 5. Separation of a complex system into d- and q-axis components. 

(24) 

so that the closed-loop system has the desired state response. 

The actual gains and may then be found using (20) and 

(21), respectively. 

C. Optimal Pole Assignment 

In this study, linear quadratic (LQ) optimal control [10] is 

used to determine the gains and , since optimal control 

frees the designer from the mathematical abstraction of pole 

assignment. Furthermore, LQ controllers offer good stability 

margins and robustness. Analyses of stability margins for discrete-time 

LQ regulators are given in [12] and [13]. 

The LQ regulator is designed by solving the algebraic Riccati 

equation to determine a gain which minimizes the quadratic 

cost function 

(25) 

and determine the quadratic cost weightings on the state 

values and inputs, respectively. The th diagonal element of 

determines the direct weighting on the th state, while off-diagonal 

elements have more complicated effects and are set to zero 

in this study. 

Some empirical guidelines for their selection can be given. 

• Heavy weighting should be placed on to ensure fast, 

well-damped transient current response. 

• The impedance of the capacitor is fairly high and little current 

is shunted through ; thus and will behave similarly, 

and an equal cost should also be placed on . 

• should be allowed to move as dictated by the grid in 

order to avoid converter saturation. Low or zero weighting 

may be placed on this state. 

• Weighting on should initially be close to or at zero. 

While an increase in this weighting will limit the amount 

of control effort used, it will also decrease damping and 

stability. For the same reason, input weighting should 

initially be set to one. 

• A fairly high weighting should be placed on the integrator 

state , in order to attain high bandwidth. However, this 

increase comes at the expense of stability. 

The transient response of the converter terminal voltage 

should be verified during a 1 per-unit step in , to ensure that 

it lies within the available converter terminal voltage, including 

the voltage required to reject the bus voltage . may be 

limited by increasing either the weighting on or the input 

weighting . 

D. Separation of and Axes 

To implement and simulate the system, the controller and 

model must be decomposed into real-valued d and -axis systems. 

The result of a multiplication between vector and 

matrix can be separated into and components using the 

matrix equation 

(26) 

This process is shown graphically in Fig. 5. Equation (26) can 

be applied to every gain in Fig. 3 to find real-valued, coupled 

- and -axis controllers, and to the matrices of the closed-loop 

state model for simulation and numerical analysis. 

IV. SIMULATION RESULTS 

To verify the controller’s performance, an LCL-filter was designed 

following the guidelines presented in [14]. The sampling 

and switching frequencies were 8 kHz and 4 kHz, respectively, 

and the filter parameters were 1.0 mH 0.04 p.u.), 

0.5 mH 0.02 p.u. , 14 F 20 p.u. , 

with a resonant frequency of 2.3 kHz. The 60 Hz, 1.4 kVA test 

system had a rated voltage of 115 V (line–line rms). 

Following the guidelines of Section III-C, the following LQ 

weightings were chosen: 

The per-unitization of and with base voltage 115 V 

and current 7 A can be done by writing and in terms 

of their per-unit values and 

(27) 

(28)


where 

Substituting (27) and (28) into (25), rearranging the result in the 

form 

(29) 

and solving for the per-unitized weightings 

yielded the following equations: 

and 

Fig. 6. Internal d-axis signals during 10-A step in I . 

(30) 

(31) 

The inverse relationships can be used to determine corresponding 

LQ weightings for any system of base values. 

The deadbeat current gains , , and were calculated 

using (17)–(19). The LQR weightings and were used to 

numerically calculate and . Finally, (20) and (21) were 

used to find and , respectively, completing the control 

design. The resulting gains are given by 

(32) 

(33) 

(34) 

(35) 

(36) 

Simulation is carried out using the closed-loop equivalent 

system, given by 

(37) 

which is valid provided the current limiter is not activated. For 

simulation, (38) was decomposed into a real-valued system with 

separate - and -axis signals using (26). 

Fig. 6 shows simulated -axis controller signals during a 10-A 

step in . 

The incremental damping current , which contains a 

decaying oscillation at the resonant frequency of the LC tank 

Fig. 7. Bode plots of i =I and i =I . 

formed by and , is subtracted from the undamped integral 

current reference to create a new reference for the 

deadbeat current controller. is made to track this deadbeat 

reference with a two-timestep delay. 

The closed-loop frequency response of the system is shown in 

the first column of Fig. 7. For this system, the theoretical bandwidth 

(at which response is 3 dB) is 646 Hz. The cross-coupling 

response, shown in the second column, is well-attenuated 

with a peak of 23 dB. It can also be seen from this figure that 

in the steady state, there is no cross-coupling response, hence 

cross-coupling has been implicitly eliminated by the complex 

-frame controller. 

V. ROBUSTNESS ANALYSIS 

The nominal eigenvalues of the overall closed-loop system 

(marked in bold on the -plane diagram of Fig. 8) show that


Fig. 8. Locus of overall closed-loop eigenvalues where L 

markers) to 39.9 mH. 

= 0.18 to 0.5 (large 

Fig. 9. Nominal pole locations of the deadbeat current controller. 

the entire system is well-damped. Since a complex-valued statespace 

model was used, the pole locations are assymetrical about 

the real axis, with each root actually representing a conjugate 

pair. 

The robustness of the controller to parameter error was analyzed 

by varying from the nominal design value of 0.5 mH, 

since the value of is highly variable due to its association 

with the grid inductance. is particularly subject to underestimation 

since the local inductance should be known to the designer. 

The percentage parameter error is defined as 

error actual value 

nominal value 

(38) 

A. Overall System Robustness 

The robustness of the overall closed-loop system is 

demonstrated in the closed-loop root-locus of Fig. 8, in 

which is varied from 0.18 mH (error 64%) to 39.9 mH 

(error 7880%). For large values of , the largest eigenvalues 

approach the unit circle asymptotically. From these 

results, it is clear that the system is quite robust to both underand 

over-estimation of . 

B. Deadbeat Current Controller Robustness 

When overcurrent limiting occurs, the incremental damping 

current has no effect; hence under ideal conditions, the 

outer LC tank formed by and is undamped and only the 

deadbeat current controller is in operation, with the closed-loop 

poles shown in Fig. 9. 

However, the second-order effect of a parameter error in 

can shift the undamped poles from the unit circle, possibly 

leading to an unstable deadbeat current controller in the event 

of overcurrent limiting. Fig. 10 shows the root-locus of the 

deadbeat current controller in the upper-right quadrant as the 

underestimation error of is increased from 0% to 100%, 

Fig. 10. Root locus of the deadbeat controller with 0100 %errorL 0% 

at f =f = f4; 4:7; 6g. Large X’s show nominal pole locations. 

for where is the filter’s resonant frequency. 

For 4, the pole becomes unstable for small 

errors in . However, for , the damping 

increases as the underestimation increases. Thus there exists a 

frequency ratio beyond which any underestimation of will 

lead to greater damping. 

It has been empirically found that if 5.8, then the 

deadbeat controller will be guaranteed to have poles with radii 

1 for any underestimation of , guaranteeing stable operation 

during overcurrent limiting. Fig. 11 shows the maximum radii 

of the deadbeat current controller poles for errors in between 

0 and 400%, where nominal values of and vary between 

0.252 mH and 12.6 mH. Filter capacitance was fixed at 14 F 

and the switching frequency was selected to yield 5.8. 

It can be seen that the maximum radius is unity for all combinations 

of inductances, showing that any underestimation of 

will cause the outermost poles to either remain along the


, damping and inte- 

Fig. 13. d- and q-axis currents during a 10-A step in i 

grator loops disabled. 

Fig. 11. Maximum eigenvalue radii of the deadbeat controller for 0400% 

%errorL 0%, C = 14 F, f =f = 5.8. 

Fig. 12. Implemented control structure. 

Fig. 14. Oscilloscope phase A signals during a 10-A step in i , damping and 

integrator loops disabled. Time: 5 ms/div. Top to bottom: i (20 A/div), i 

(20 A/div), v (100 V/div), v (100 V/div). 

unit circle or move towards the origin. Moreover, the addition 

of conduction losses will also increase system damping, thus the 

frequency ratio of 5.8 is a conservative requirement. 

VI. EXPERIMENTAL RESULTS 

The controller was implemented on a Texas Instruments 

TMS320C40 DSP as shown in Fig. 12. 

All measurements are first converted to the -frame, then 

projected onto the -frame synchronized to the 115-V bus 

voltage . The synchronization signal is obtained 

by lowpass filtering and phase-advancing the result by 

to compensate for filter, sensor and data-acquisition delays. 

Based on the user reference , the -frame controller 

then calculates the voltage command vector , which is 

converted back to a three-phase vector and sent to an Altera 

Flex 8000 FPGA, which generates and sends the corresponding 

PWM gating signals to the converter. Converter switching is 

performed by a 50-A, 1200-V six-pack IGBT module. The 

converter dc link capacitance is 4800 F, and is connected to 

a 50-kW, 220-V dc generator. 

A. Step Response 

Fig. 13 shows and during a 10-A step in , employing 

only the inner deadbeat current loop. The response is 

nearly deadbeat, with only a small amount of cross-coupling due 

to unmodeled source inductance. As shown in the oscilloscope 

traces of Fig. 14, severe ringing is observed in and since 

the LC tank consisting of capacitor and inductor is not 

damped. In addition, there is a 4-kHz harmonic modulated by 

a sixth harmonic appearing in the -frame currents, which can 

be attributed to: 1) bandwidth limitations of the current sensors 

and data acquisition, 2) asymmetries resulting from the on-state 

voltage drop of the switches, and 3) asymmetries in the deadtime 

insertion algorithm. This distortion does not significantly 

affect the output. 

Fig. 15 shows the controller’s step response with the damping 

and integrator loops enabled. The rise time is approximately 

1.5 ms, there is no cross-coupling, and as expected, the actual 

currents and follow their respective deadbeat references 

and within approximately two timesteps. The step response 

characteristics closely resemble the simulated results of 

Fig. 6, validating the model. The oscilloscope image of Fig. 16


Fig. 15. d- and q-axis currents during a 10-A step in I , damping and integrator 

loops enabled. 

Fig. 17. d- and q-axis currents, and three-phase bus voltages during three-phase 

fault. 

Fig. 16. Oscilloscope phase A signals during a 10-A step in I , damping and 

integrator loops enabled. Time: 5 ms/div. Top to bottom: i (20 A/div), v 

(100 V/div), i (20 A/div), v (100 V/div). 

Fig. 18. Oscilloscope screen capture of phase A signals during three-phase 

fault. Time: 5 ms/div. Top to bottom: i (10 A/div), v (100 V/div), i 

(10 A/div), v (100 V/div). 

shows that the step response is fast, the system is well-damped, 

and there is no ringing. 

B. Disturbance Rejection 

In order to demonstrate the ability of the controller to reject 

disturbances and its ability to damp the resonance from excitation 

by external sources, a balanced three-phase fault was introduced 

which instantaneously reduced the magnitude of 

by approximately 2/3 for 15 ms before being cleared. The response 

of the system to this fault is shown in Figs. 17 and 18. 

There is a brief transient in due to the speed of the fault exceeding 

the controller bandwidth, and because of the approximation 

in the calculation of the feedforward gain. 

Otherwise, the system is well-damped despite the high speed 

and severity of the fault, as shown in the oscilloscope screen capture 

of Fig. 18. Despite imbalances caused by different clearing 

times for each phase, the controller maintains good regulation, 

demonstrating its ability to operate in an unbalanced system. 

C. Overcurrent Protection 

The current controller regulated the current during the fault 

so effectively that overcurrent limits were rarely reached. As 

a result, this controller could not be used to test the overcurrent 

protection. However, use of a less aggressive controller or 

a larger filter capacitor will make overcurrent limiting imperative. 

Fig. 19 shows the sampled and calculated - and -axis currents 

for a less aggressive damping controller during the fault, 

with the current limits set to 30 A in each axis. It can be seen 

that this controller allows high current levels to occur for a significant 

period of time. Despite the change in overall gain, the 

deadbeat controller maintained the same performance, tracking 

its reference with a fixed delay. Fig. 20 shows the corresponding 

phase A currents and voltages. 

The overcurrent limit was then set to 10 A in each axis and the 

balanced, three-phase fault was reintroduced to demonstrate the 

transient overcurrent protection capabilities of the controller. As 

shown in Fig. 21 the -axis current reaches the new overcurrent 

limit immediately after the fault but is clipped to 10 A. Ringing 

can be seen in the oscilloscope traces of and of Fig. 22 

following the fault. This occurs when the current is clipped because 

the sum of the damping and integral feedback is saturated, 

thus only the deadbeat controller is in operation with the current 

limit as its reference. With the damping feedback disabled 

by saturation, the fault excites ringing in the LC tank formed


Fig. 19. d- and q-axis signals and three-phase bus voltages during three-phase 

fault with less aggressive control gains, 30-A current limit. 

Fig. 21. d- and q-axis signals and three-phase bus voltages during three-phase 

fault with less aggressive control gains, 10-A current limit. 

Fig. 20. Oscilloscope phase A signals during three-phase fault with less aggressive 

control gains, 30-A current limit. Time: 5 ms/div. Top to bottom: i 

(20 A/div), v (100 V/div), i , (20 A/div), v (100 V/div). 

Fig. 22. Oscilloscope phase A signals during three-phase fault with less aggressive 

control gains, 10-A current limit. Time: 5 ms/div. Top to bottom: i 

(20 A/div), v (100 V/div), i (20 A/div), v (100 V/div). 

by and , which will resonate just as if no converter were 

present. On the other hand, the converter is protected and can 

ride through the fault without tripping. 

D. Frequency Response 

The measured frequency response of the controller is shown 

in Fig. 23. The actual bandwidth (the 3 dB frequency) of the 

controller was approximately 430 Hz. This value is 67% of 

the theoretical bandwidth. The decrease is mainly attributed to 

the frequency-dependent parameters of the ac inductors. Parameter 

errors may also have contributed to detuning of the controller. 

In addition to the faster high-frequency roll-off, there 

was also an unexpected low frequency offset of approximately 

0.5 dB. The cause may simply be due to aliasing of the harmonically 

rich output current, but this discrepancy does not invalidate 

these results. 

VII. CONCLUSION 

In this study, a rigorous discrete-time model of an LCL-filtered 

converter including calculation delay was derived in the 

-frame. By using a complex state-space, control design was 

Fig. 23. Magnitude frequency response of the test system controller, compared 

to theoretical values. 

simplified. The complex model was used to design a controller 

which implicitly eliminated -axes cross-coupling, and for the


first time combined the flexibility of pole assignment with inherent 

transient overcurrent protection. -plane analysis of a test 

system with characteristic parameters showed that the controller 

was robustly stable to variations in the grid interface inductance. 

Both simulation and experimental results showed that even at 

a low switching frequency relative to the resonant frequency, 

the proposed control structure can achieve well-damped, highbandwidth 

current control, and that cross-coupling can be minimized. 

Furthermore, the controller has good disturbance rejection, 

and regardless of overall performance provides instantaneous 

overcurrent protection even during severe transient disturbances. 

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Eric Wu (S’03–M’05) was born in Taipei, Taiwan, R.O.C., in 1978. He received 

the B.A.Sc. and M.A.Sc. degrees in electrical engineering from the University 

of Toronto, Toronto, ON, Canada, in 2002 and 2005, respectively. 

Peter W. Lehn (SM’05) received the B.Sc. and M.Sc. degrees in electrical enginnering 

from the University of Manitoba, Winnipeg, MB, Canada, in 1990 

and 1992, respectively, and the Ph.D. degree from the University of Toronto, 

Toronto, ON, Canada, in 1999. 

From 1992 to 1994, he was with the Network Planning Group, Siemens AG, 

Erlangen, Germany. Presently, he is an Associate Professor at the University of 

Toronto.

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