Analysis and design of a 200W LDMOS based doherty amplifier for ...

e lost when the Doherty amplifier is operating below its
transition point. It is therefore necessary to add a driver
stage to maximize efficiency. A driver is also added to the
main amplifier to accommodate shaping of the transfer
characteristics, which is critical in a Doherty amplifier.
The splitter asymmetry (A) is set by the gain difference:
A=G,-G, (9)
The gain of the total Doherty amplifier, at full power, can
then be determined from:
Gm, - 3 +GI - IOlog(l+ (10)
In order to maintain a constant gain over power for the
total Doherty amplifier, the gain characteristics (AWAM)
of the peak amplifier should be matched to that of the
main amplifier, and,can be determined from:
G, = 101og(lO"'lo(l+ IOd~~o)-lOG1po)- A (1 1)
The amplifiers are designed using internally matched
Philips LDMOS transistors. In order to get maximum
efficiency improvement in a Doherty amplifier the
transistors need to have specific properties. The transistor
for the peak amplifier should he designed to have a high
off-state output impedance and exhibit low reverse RF
drive. For the main amplifier the transistor should he able
to provide maximum performance under the load pulling
conditions.
The implementation of the two-stage class-AB main
amplifier, using two BLF2022-40 (5OWpeak) in the final
stage and one BLF2043(10W) in the driver stage, is
shown in Fig. 5. The final stage devices are paralleled
without using a quadrature combiner, since both
transistors must experience in-phase load-pulling for
Doherty operation. The interstage matching is designed to
meet the bandwidth requirement of 60MHz and to obtain
approximately 3dB compression required for Doherty
operation.
Fig. 5. Class-AB main amplifier implementation.
The resulting M AM and AMPM characteristics for a
50n load are shown in Fig. 6 with a peak power capability
of 1oow.
Poldhl
Fig. 6. AM-AM and AM-PM characteristics of the class-AB
main amplifier for a 5011 load:
The implementation of the two-stage class-C peak
amplifier is shown in Fig. 7. It utilizes two BLF2022-40 in
the final stage and one similar device in the driver stage.
The interstage circuit not only provides impedance
matching but also the correct phase matching between the
driver output and final stage input in order to obtain a
predistortion effect that aligns the M AM and AM/PM
characteristics of the peak amplifier with main amplifier.
The resulting M AM and AWM characteristics for a
50n load are shown in Fig. 8 with a peak power capability
of 1oow.
Fig. 7. Class-C peak amplifier implementation.
X I I I I I I I -,&a
0 . . . . .. . .. .. . . -155
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hldbl
Fig. 8. AM-AM and AM-PM characteristics of the class-C peak
amplifier for a 5On load.
Fig. 9 shows the circuit diagram of the total Doberty
implementation. The transmission lines TL3 and TL4 are
used to maximize overall efficiency. TL3 provides the
phase matching to rotate the off-state impedance of the
peak amplifier to a high impedance level at the combining
point between TL5 and TL6. TL4 provides the phase
matching to ensure that a resistive load of twice the
nominal value is presented at the die level of the main PA
transistors. The input utilizes an asymmetrical (5dB)
branch line coupler as a splitter. TLl and TJ2 are added to
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