Hardware \in the Loop" Simulation with COSSAP: Closing the ... - ICE

chips are tted on standard device adaptors rather than
device specic ones, which are needed in our case. This
increases the interface complexity sincepower and ground
pins need to be congurable, but eases the setup. However,
for complete systems rather than single chips special
device adaptors are still required. The hardware modelers
can handle bidirectional as well as unidirectional device
ports. They are stand alone ethernet devices and some
communication overhead is the price for obtaining a hardware
modeler which is independent of the simulation workstation
architecture. Current product information led to
the estimate that no simulation speedup would have been
possible in the simulation of DIRECS. Current pricing for
hardware modelers is well above US$ 100.000 and development
kits to integrate the hardware modelers into existing
simulation environments are very expensive too.
5 Conclusion
While hardware modeling in copnjunction with eventdriven
simulation is a commercial reality, our experimental
setup shows that hardware modeling is possible in conjunction
with data ow driven simulations. This is due to
the fact that we deal with the sequence of meaningful values
rather than timed signals. Furthermore, the class of
hardware components which can be handled was restricted
to fully synchronous components with static memory
to avoid recording and playing stimuli historys. We did
not support bidirectional ports. These restrictions reect
our application domain which is in the loop simulation
of digital signal processing ASICs for performance verication.
An experimental hardware modeling solution for
the simulation system COSSAP was developed in conjunction
with a proprietary test environment forintegrated
circuits and VLSI systems. This solution provides the full
functionality for hardware modeling of the envisaged class
of hardware components at high simulation speed and low
cost. It turned out during runtime proling that in our implementation
the small wordlength of the hostinterface is
the remaining bottleneck but the interface model provides
already a throughput at which simple additional software
models are the speed limiting factor.
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