Current Induced Failure Analysis of Ni-based Microinsert ...

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Current Induced Failure Analysis of Nibased
Microinsert
Interconnections for Flip Chip Die on Wafer
Attachment.
V. Mandrillon, A. Reverdy, D. Arias
G.Tartavel, H.Boutry

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Overview
• Introducing of CEA- LETI Nickel Micro insert Wafer level stacking
technology & experimental set-up
• Implementing of specific reliability characterization and reviewing
results
• Failure Analysis : qualifying lock-in Thermography to localize failures
• Tests have been performed on few samples to investigate analysis
flow

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CEA-LETI, Nickel Micro insert Wafer level stacking technology :
32 contacts daisy chains test system
1- Epoxy Glue dispense
2- Flip Chip assembly
4 x 4 Ni insert
contact matrix
( 6 µm)
3- Thermo-compression
- 40 N per chip 70 mN per Ni Micro insert
- Epoxy Curing 180 °C during 10 minutes

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Electrical contact analysis
Design of the 32 contacts daisy chain test samples – enabling electrical
characterization

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Good die selection after parametric test
Good dies have been selected for the following reliability study

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Reliability Characterization
Current / temperature stress setup
> Reliability study has been adapted to technology specifications
•The voltage versus current characteristics of the daisy chain is linear at least up to 500 mA
and up to 100°C .
•The Resistance value of the contacts change by 20 % between 3 and 3.7 mOhm when the
contact undergoes a temperature increase between ambient and 100°C . This phenomenon is
reversible and can be attributed to the temperature dependence resistivity of the materials.

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Current Stress tests & Failures (1/2)
Current stress tests for [A] 100°C at 500 mA and [B] 100°C at 750 mA
Characterization of the corresponding failure mechanisms
A. A failure of the stack is created under a 500 mA current stressing at 100°C after stress
durations ranging between 50 to 150 hours.
B. A failure of the stack is created in a few tens of seconds under a 750 mA current
stressing at 100°C.

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Current Stress tests & Failures (2/2)
Detailed segmented monitoring of the 32 contacts daisy chain failure at 500 mA
DC set-upconstant
current
Different
Segments of
daisy chain
Tension (V)
2- Higher
resistance
1- Open
Time (h)
2 failure types
1- Failure of contact n° 1 typical for electromigration
2- Degradation of electrical contact resistance in segments :
4 to 8 and 8 to 12
Next:
localizing
faults

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2
Failure Analysis solution - Fault localization using Lock-in
Thermography
• Non Destructive “Through
package” solution
> Using Lock-in Thermography
V
Simplification of Lockin
Thermography
technology
IR-image (V = off)
IR-image (V = on)
“on-images” – “off-images”
V
1
xy defect
localization
t p
(f lock-in
)
only temperature
differences are detected
t surface
0
IR images impacted by emissivity and not
enough sensitive – no fault detection
t
thermal delay
defect depth (z)
* Acknowledgements to CIMPACA to enable access to ELITE system

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Why and When Lock-in Thermography – and technology
requirement for 3D package
• Lock-in Thermography is
based on electrical
activation of the fault
• Sensitivity & Resolution are
required for 3D packages
– Multiples publications in
ESREF/ ISTFA
• Finding fault in 3D stack!
• Lock-in Thermography also
enables:
Thermal design support
(identifying hot spot)
Complementary defect
localization technique on
silicon
“emissivity”
measurment
Not Enough
Sensitivity
Need Lock-in
analysis
Need camera
sensitivity
Lock-In
Thermography
Hot Spot detected
Enough Sensitivity

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Fault localization using IR lock in thermography
Localization of the daisy chain failure at 500 mA
Chip B7 Lock-in thermography imaging (0,5Hz,
20min, 1V – 125mA) – thresholded phase image
superimposed on basic IR image
Lock in thermography allows localization of resistance
degradation of contact n° 5 and n° 10
> Sensitive to low resistive faults
* Acknowledgements to CIMPACA to enable access to ELITE system

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Fault localization using IR lock in thermography
Localization for the daisy chain failure at 750mA (1/2)
IR image quality
impacted by
surface quality
Lock in thermography allows
localization of resistance degradation
of contacts n° 5 , 8, 9, 10, 14 and 19
Chip C9 Lock-in thermography imaging (0,5Hz, 2min, 1V – 6mA)
– thresholded amplitude image superimposed on basic IR image
Phase image support
analysis – indicating
different ‘time delay’
> Differentiating a failure
on the top vs on the
bottom
Phase images - 5x lens (0, 3µm pixel),
0.5Hz lock in frequency, 3 min @
500mV
* Acknowledgements to CIMPACA to enable access to ELITE system

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Fault localization using IR lock in thermography
Localization for the daisy chain failure at 750mA (2/2)
> Resolution sufficient to resolve single vs multiple failure micro-pillar
IR image quality
impacted by
surface quality
Overlay of topology image, with amplitude image 10x lens,
0.5Hz lock in frequency, 5 min @ 500mV

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Default cross section analysis
SEM imaging at failure location for failure analysis ( 750 mA stress current)
IR image quality
impacted by
surface quality
• 750 mA stressing seems to show delamination rather than electromigration
Local heating

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Conclusion
• CEA- LETI Nickel Micro insert Wafer level stacking technology is
mature
• Reliability study adapted to this technology
• Lock-in Thermography enable fault localization through package
– Providing sufficient sensitivity to low resistive fault
• Following reliability study will support better characterization of fault
mechanisms