M32C/83 Group Hardware Manual - TE-EPC-LPC

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M32C/83 Group 8. Clock Generating Circuit 8.2 CPU Clock and BCLK The CPU operation clock is referred to as the CPU clock. The CPU clock is also the count source for the watchdog timer. After reset, the CPU clock is the main clock divided-by-8. In memory expansion or microprocessor mode, the clock having the same frequency as the CPU clock can be output from the BCLK pin as BCLK. Refer to 8.4 Clock Output Function for details. The main clock, sub clock, on-chip oscillator clock or PLL clock can be selected as a clock source for the CPU clock. Table 8.3 shows CPU clock source and bit settings. When the main clock, on-chip oscillator clock or PLL clock is selected as a clock source of the CPU clock, the selected clock divided-by-1 (no division), -2, -3, -4, -6, -8, -10, -12, -14 or -16 becomes the CPU clock. The MCD register selects the clock division. When the microcomputer enters stop mode or low-power consumption mode (except when the on-chip oscillator clock is the CPU clock), the MCD register is set to "0816" (divide-by-8 mode). Therefore, when the main clock starts running, the CPU clock enters middle-speed mode (divide-by-8). Table 8.3 CPU Clock Source and Bit Settings CPU Clock Source CM0 Register CM2 Register CM1 Register CM07 CM21 CM17 Main Clock 0 0 0 Sub Clock 1 0 0 On-chip Oscillator Clock 0 1 0 PLL Clock 0 0 1 8.3 Peripheral Function Clock The peripheral function clock becomes the operation clock or count source for peripheral functions excluding the watchdog timer. 8.3.1 f1, f8, f32 and f2n f1, f8, f32 and f2n are the main clock (1) or on-chip oscillator clock divided-by-1, -8, -32 ,or -2n (n=1 to 15. No division when n=0). The CM21 bit determines which clock is selected. When the CM02 bit is set to "1" (peripheral function stops in wait mode) when entering wait mode, f1, f8, f32 and f2n stop running. These clocks also stop in low-power consumption mode. f1, f8 and f2n are used as the operation clock for the serial I/O and the count source for timers A and B. The CNT3 to CNT0 bits in the TCSPR register selects a f2n division. f1 is also used as the operation clock for the intelligent I/O. The CLKOUT pin outputs f8 and f32 . Refer to 8.4 Clock Output Function for details. 8.3.2 fAD fAD is the operation clock for the A/D convertor and has the same frequency as the main clock (1) and onchip oscillator clock. The CM21 bit determines which clock is selected. When the CM02 bit is set to "1" (peripheral function stop in wait mode) when entering wait mode, fAD stops. fAD also stops in low-power consumption mode. NOTES: 1. When the CM17 bit is set to "1" (PLL clock as CPU clock source), the PLL clock is the main clock. Rev. 1.20 Jun. 01, 2004 REJ09B0034-0120Z Page 81 of 477
M32C/83 Group 8. Clock Generating Circuit 8.3.3 fC32 fC32 is the sub clock divided by 32. fC32 is used for as a count source for the timers A and B. fC32 is available when the sub clock is running. 8.4 Clock Output Function The CLKOUT pin outputs fC, f8 or f32. In memory expansion and microprocessor modes, a clock having the same frequency as the CPU clock can be output from the BCLK pin as BCLK. Table 8.4 lists CLKOUT pin function in single-chip mode. Table 8.5 lists CLKOUT pin functions in memory expansion and microprocessor modes. Table 8.4 CLKOUT Pin in Single-Chip Mode PM0 Register (1) CM0 Register (2) PM07 CM01 CM00 1 1 1 0 0 1 1 0 1 0 1 CLKOUT Pin Function P53 I/O port Outputs fc Outputs f8 Outputs f32 - : Can be set to either "0" or "1" NOTES: 1. Rewrite the PM0 register after the PRC1 bit in the PRCR register is set to "1" (write enable) 2. Rewrite the CM0 register after the PRC0 bit in the PRCR register is set to "1" (write enable) Table 8.5 BLCK/CLKOUT Pin in Memory Expansion Mode and Microprocessor Mode PM1 Register (1) PM15 PM14 002, 102, 112, PM0 Register (1) CM0 Register (2) PM07 CM01 CM00 0 1 1 0 (3) 0 0 0 (3) 0 1 1 1 1 1 Outputs BCLK Outputs "L" (not P53) Outputs fc Outputs f8 0 1 0 (3) Outputs ALE - : Can be set to either "0" or "1" NOTES: 1. Rewrite the PM0 and PM1 register after the PRC1 bit in the PRCR register is set to "1" (write enable) 2. Rewrite the CM0 register after the PRC0 bit in the PRCR register is set to "1" (write enable) 3. When the PM07 bit is set to "0" (selected in the CM01 to CM00 bits) or the PM15 to PM14 bits are set to "012" (P53/BCLK), set the CM01 to CM00 bits to "002" (I/O port P53) 8.5 Power Consumption Control Normal operation mode, wait mode and stop mode are provided as the power consumption control. All mode states, except wait mode and stop mode, are called normal operation mode in this document. Figure 8.14 shows a block diagram of status transition in wait mode and stop mode. Figure 8.15 shows a block diagram of status transition in all modes. 0 1 0 (3) CLKOUT Pin Function Outputs f32 Rev. 1.20 Jun. 01, 2004 REJ09B0034-0120Z Page 82 of 477
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REJ09B0034-0120Z 16/32 M32C/83 Grou
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How to Use This Manual 1. Introduct
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Table of Contents Quick Reference b
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10.1 Types of Interrupts ..........
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16.2.2 Serial Data Logic Inverse Fu
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22.1.16 CAN0 Message Slot i Control
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27.8.3 Timer B ....................
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Quick Reference by Address Address
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M32C/83 Group 1. Overview 1.2 Perfo
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M32C/83 Group 1. Overview 1.3 Block
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M32C/83 Group 1. Overview 1.5 Pin A
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M32C/83 Group 1. Overview 1.6 Pin D
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M32C/83 Group 1. Overview Table 1.6
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M32C/83 Group 1. Overview Table 1.6
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M32C/83 Group 2. Central Processing
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M32C/83 Group 2. Central Processing
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M32C/83 Group 4. Special Function R
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M32C/83 Group 13. DMACII 13.4.4 Cha
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M32C/83 Group 14. Timer 14. Timers
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M32C/83 Group 14. Timer (Timer A) 1
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M32C/83 Group 14. Timer (Timer A) T
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M32C/83 Group 14. Timer (Timer A) W
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M32C/83 Group 14. Timer (Timer B) T
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M32C/83 Group 14. Timer (Timer B) 1
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M32C/83 Group 15. Three-Phase Motor
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M32C/83 Group 16. Serial I/O RxDi S
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M32C/83 Group 16. Serial I/O UARTi
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M32C/83 Group 16. Serial I/O Extern
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M32C/83 Group 16. Serial I/O (Clock
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M32C/83 Group 16. Serial I/O (UART)
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M32C/83 Group 16. Serial I/O (Speci
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M32C/83 Group 17. A/D Converter 17.
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M32C/83 Group 17. A/D Converter 000
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M32C/83 Group 17. A/D Converter A/D
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M32C/83 Group 18. D/A Converter 18.
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M32C/83 Group 18. D/A Converter D/A
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M32C/83 Group 19. CRC Calculation C
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0 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b1
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M32C/83 Group 21. Intelligent I/O 2
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M32C/83 Group 21. Intelligent I/O R
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M32C/83 Group 21. Intelligent I/O R
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M32C/83 Group 21. Intelligent I/O G
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M32C/83 Group 21. Intelligent I/O (
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M32C/83 Group 21. Intelligent I/O 2
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M32C/83 Group 22. CAN Module 22. CA
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M32C/83 Group 22. CAN Module 22.1 C
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M32C/83 Group 22. CAN Module NOTES:
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M32C/83 Group 22. CAN Module 22.1.3
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M32C/83 Group 22. CAN Module CAN0 G
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M32C/83 Group 22. CAN Module CAN0 M
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M32C/83 Group 22. CAN Module CAN0 M
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M32C/83 Group 22. CAN Module CAN bu
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M32C/83 Group 22. CAN Module CAN0 s
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M32C/83 Group 23. DRAMC DRAM Contro
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M32C/83 Group 23. DRAMC (1) In 8-bi
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M32C/83 Group 23. DRAMC (1) Read cy
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M32C/83 Group 24. Programmable I/O
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M32C/83 Group 26. Electrical Charac
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M32C/83 Group Table 26.3 Electrical
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M32C/83 tc w w tr tf Symbol Group P
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M32C/83 Group Timing Requirements (
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M32C/83 Group Switching Characteris
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M32C/83 Group Table 26.24 Electrica
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M32C/83 Group Timing Requirements (
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M32C/83 Group 27. Precautions (Bus)
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M32C/83 Group 27. Precautions (Cloc
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M32C/83 Group 27. Precautions (Prot
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M32C/83 Group 27. Precautions (Inte
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M32C/83 Group 27. Precautions (Time
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M32C/83 Group 27. Precautions (Time
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M32C/83 Group 27. Precautions (Seri
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M32C/83 Group 27. Precautions (A/D
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M32C/83 Group 27. Precautions (Inte
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M32C/83 Group 27. Precautions (Flas
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M32C/83 Group 27. Precautions (Low
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M32C/83 Group Package Dimensions 10
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M32C/83 Group Register Index G G0BC
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REVISION HISTORY M32C/83 GROUP HARD
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2-6-2, Ote-machi, Chiyoda-ku, Tokyo
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