M32C/83 Group Hardware Manual - TE-EPC-LPC

M32C/83
Group
13. DMACII
13.4.4 Chained Transfer
The CHAIN bit in MOD selects the chained transfer.
The following process initiates the chained transfer.
(1) Transfer, caused by a transfer request factor, occurs according to the content of the DMAC II index.
The vectors of the request factor indicates where the DMAC II index is allocated. For each request, the
BRST bit selects either single or burst transfer.
(2) When COUNT reaches "0", the contents of CADR1 to CADR0 are written to the vector of the request
factor. When the INTE bit in the MOD is set to "1," the end-of-transfer interrupt is generated simultaneously.
(3) When the next DMAC II transfer request is generated, transfer occurs according to the contents of the
DMAC II index indicated by the vector rewritten in (2).
Figure 13.4 shows the relocatable vector and DMACII index of when the chained transfer is in progress.
When performing the chained transfer, the relocatable vector table must be located in the RAM.
INTB
RAM
Relocatable vector
Peripheral I/O interrupt vector causing DMAC II request
Default value of DMAC II is BASE(1).
DMAC II
Index(1)
BASE(1)
(CADR1 to
CADR0)
BASE(2)
The above vector is rewritten to BASE(2)
when a transfer is completed.
Starts at BASE(2) when next request conditions
are met.
Transferred according to the DMAC II Index.
DMAC II
Index(2)
BASE(2)
(CADR1 to
CADR0)
BASE(3)
The above vector is rewritten to BASE(3)
when a transfer is completed.
Figure 13.4 Relocatable Vector and DMAC II Index
13.4.5 End-of-Transfer Interrupt
The INTE bit in MOD selects the end-of-transfer interrupt. Set the starting address of the end-of-transfer
interrupt routine in the IADR1 to IADR0 bits. The end-of-transfer interrupt is generated when COUNT
reaches "0."
Rev. 1.20 Jun. 01, 2004
REJ09B0034-0120Z
Page 132 of 477