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M32C/83 Group Hardware Manual - TE-EPC-LPC

M32C/83 Group Hardware Manual - TE-EPC-LPC

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<strong>M32C</strong>/<strong>83</strong><br />

<strong>Group</strong><br />

23. DRAMC<br />

(1) Read cycle (WT bit = 1 with 1 wait state)<br />

BCLK<br />

MA0 to MA12<br />

Row<br />

address<br />

Column<br />

address 1<br />

Column<br />

address 2<br />

Column<br />

address 3<br />

Column<br />

address 4<br />

RAS<br />

CASH<br />

CASL<br />

'H'<br />

DW<br />

D0 to D15<br />

(EDO mode)<br />

NO<strong>TE</strong>S:<br />

1. With an 8-bit data bus, only CASL outputs a data enabled to read. CASH outputs an indeterminate data.<br />

(2) Write cycle (WT bit = 1)<br />

BCLK<br />

MA0 to MA12<br />

Row<br />

address<br />

Column<br />

address 1<br />

Column<br />

address 2<br />

Column<br />

address 3<br />

Column<br />

address 4<br />

RAS<br />

CASH<br />

CASL<br />

DW<br />

D0 to D15<br />

NO<strong>TE</strong>S:<br />

1. With an 8-bit data bus, only CASL outputs a data enabled to read. CASH outputs an indeterminate data.<br />

Figure 23.4 Bus Timing during DRAM Access (2)<br />

Rev. 1.20 Jun. 01, 2004<br />

REJ09B0034-0120Z<br />

Page 364 of 477

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