M32C/83 Group Hardware Manual - TE-EPC-LPC

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M32C/83 Group 25. Flash Memory Version 25.3.5.8 Read Lock Bit Status Command The read lock bit status command reads the lock bit state of a specified block. By writing "xx7116" in the first bus cycle and reading the highest-order address (however, A0=0) of a block in the second bus cycle, the lock bit state information of a specified block is read out to the data bus (D6). Figure 25.10 shows a flow chart of the read lock bit status command programming. Start Write command code "xx7116" Read the value in the highest-order block address D6 = 0 NO YES Blocks are locked No block is locked Figure 25.10 Read Lock Bit Status Command Rev. 1.20 Jun. 01, 2004 REJ09B0034-0120Z Page 403 of 477
M32C/83 Group 25. Flash Memory Version 25.3.6 Full Status Check If an error occurs when a program or erase operation is completed, the SR3 to SR5 bits in the status register are set to "1", indicating a specific error. Therefore, execution results can be confirmed by checking these bits (full status check). Table 25.5 lists errors and status register state. Figure 25.12 shows a flow chart of the full status check and handling procedure for each error. Table 25.5 Errors and Status Register State Status Register Error Error Occurrence Conditions SR5 SR4 SR3 1 1 0 Command sequence error • An incorrect command is written • A value other than "xxD016" or "xxFF16" is written in the second 1 0 0 Erase error bus cycle of the lock bit program, block erase or erase all unlocked block command (1) • The block erase command is executed on a locked block 2 0 1 0 Program error • The block erase or erase all unlocked block command is executed on an unlock block but the erase operation is not completed as expected • The page program command is executed in a locked 0 0 1 Excessive write error block (2) • The page program command is executed in an unlocked block but the program operation is not completed as expected • The lock bit program command is executed but the program operation is not completed as expected Excessive write occurs after the page program command is executed NOTES: 1. The flash memory enters read array mode when command code "xxFF16" is written in the second bus cycle of these commands. The command code written in the first bus cycle becomes invalid. 2. If the FMR02 bit is set to "1" (lock bit disabled), no error occurs even under the conditions listed above. Rev. 1.20 Jun. 01, 2004 REJ09B0034-0120Z Page 404 of 477
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REJ09B0034-0120Z 16/32 M32C/83 Grou
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How to Use This Manual 1. Introduct
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Table of Contents Quick Reference b
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10.1 Types of Interrupts ..........
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16.2.2 Serial Data Logic Inverse Fu
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22.1.16 CAN0 Message Slot i Control
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27.8.3 Timer B ....................
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Quick Reference by Address Address
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M32C/83 Group 1. Overview 1.2 Perfo
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M32C/83 Group 1. Overview 1.3 Block
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M32C/83 Group 1. Overview 1.5 Pin A
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M32C/83 Group 1. Overview 81 82 83
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M32C/83 Group 1. Overview 1.6 Pin D
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M32C/83 Group 1. Overview Table 1.6
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M32C/83 Group 1. Overview Table 1.6
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M32C/83 Group 2. Central Processing
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M32C/83 Group 2. Central Processing
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M32C/83 Group 4. Special Function R
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M32C/83 Group 5. Reset 5. Reset Har
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M32C/83 Group 5. Reset ____________
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M32C/83 Group 6. Processor Mode 6.
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M32C/83 Group 6. Processor Mode Pro
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M32C/83 Group 7. Bus 7. Bus In memo
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M32C/83 Group 7. Bus Table 7.2 Proc
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M32C/83 Group 7. Bus Example 1: Whe
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M32C/83 Group 7. Bus 7.2.4 Bus Timi
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M32C/83 Group 7. Bus (1) Separate B
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M32C/83 Group 7. Bus 7.2.5 ALE Sign
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M32C/83 Group 7. Bus Table 7.7 Micr
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M32C/83 Group 8. Clock Generating C
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M32C/83 Group 10. Interrupts 10. In
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M32C/83 Group 10. Interrupts 10.3.2
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M32C/83 Group 10. Interrupts Table
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M32C/83 Group 10. Interrupts 10.6 I
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M32C/83 Group 10. Interrupts Interr
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M32C/83 Group 10. Interrupts Table
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M32C/83 Group 10. Interrupts ______
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M32C/83 Group 10. Interrupts 10.10
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M32C/83 Group 10. Interrupts Interr
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M32C/83 Group 11. Watchdog Timer 11
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M32C/83 Group 11. Watchdog Timer Sy
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M32C/83 Group 12. DMAC DMAC starts
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M32C/83 Group 12. DMAC Table 12.2 D
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M32C/83 Group 12. DMAC DMAi Transfe
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M32C/83 Group 12. DMAC 12.1 Transfe
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M32C/83 Group 12. DMAC 12.2 DMAC Tr
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M32C/83 Group 13. DMACII 13. DMAC I
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M32C/83 Group 13. DMACII 13.1.2 DMA
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M32C/83 Group 13. DMACII 13.1.3 Int
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M32C/83 Group 13. DMACII 13.4.4 Cha
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M32C/83 Group 14. Timer 14. Timers
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M32C/83 Group 14. Timer (Timer A) 1
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M32C/83 Group 14. Timer (Timer A) T
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M32C/83 Group 14. Timer (Timer A) W
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M32C/83 Group 14. Timer (Timer B) T
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M32C/83 Group 14. Timer (Timer B) 1
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M32C/83 Group 15. Three-Phase Motor
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M32C/83 Group 16. Serial I/O RxDi S
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M32C/83 Group 16. Serial I/O UARTi
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M32C/83 Group 16. Serial I/O Extern
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M32C/83 Group 16. Serial I/O (Clock
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M32C/83 Group 16. Serial I/O (UART)
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M32C/83 Group 16. Serial I/O (Speci
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M32C/83 Group 17. A/D Converter 17.
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M32C/83 Group 17. A/D Converter 000
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M32C/83 Group 17. A/D Converter A/D
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M32C/83 Group 18. D/A Converter 18.
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M32C/83 Group 18. D/A Converter D/A
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M32C/83 Group 19. CRC Calculation C
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0 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b1
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M32C/83 Group 21. Intelligent I/O 2
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M32C/83 Group 21. Intelligent I/O R
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M32C/83 Group 21. Intelligent I/O R
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M32C/83 Group 21. Intelligent I/O G
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M32C/83 Group 21. Intelligent I/O (
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M32C/83 Group 21. Intelligent I/O 2
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M32C/83 Group 22. CAN Module 22. CA
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M32C/83 Group 22. CAN Module 22.1 C
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M32C/83 Group 22. CAN Module NOTES:
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M32C/83 Group 22. CAN Module 22.1.3
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M32C/83 Group 22. CAN Module CAN0 G
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M32C/83 Group 22. CAN Module CAN0 M
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Page 475 and 476: M32C/83 Group 27. Precautions (Bus)
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M32C/83 Group 27. Precautions (Cloc
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M32C/83 Group 27. Precautions (Prot
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M32C/83 Group 27. Precautions (Inte
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M32C/83 Group 27. Precautions (Time
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M32C/83 Group 27. Precautions (Time
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M32C/83 Group 27. Precautions (Seri
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M32C/83 Group 27. Precautions (A/D
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M32C/83 Group 27. Precautions (Inte
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M32C/83 Group 27. Precautions (Flas
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M32C/83 Group 27. Precautions (Low
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M32C/83 Group Package Dimensions 10
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M32C/83 Group Register Index G G0BC
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REVISION HISTORY M32C/83 GROUP HARD
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2-6-2, Ote-machi, Chiyoda-ku, Tokyo
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