Self-Timed SRAM for Energy Harvesting Systems - Electronics ...

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thermal fluctuations, timing tends to be the first issue affected. Most systems are still designed with global clocking and the design is often made overly pessimistic to avoid failures due to Vdd (timing) variations. Along with the advent of the nanometre CMOS technology, the continuation of this scaling process is vital to the future development of the digital industries. The International Technology Roadmap for Semiconductors (ITRS) [1] predicts poorer scaling for wires than transistors in future technology nodes. This makes the above worst timing assumption even worse along with power supply voltage drooping [17]. Asynchronous techniques may provide solutions to all these problems. Unlike synchronous systems, asynchronous designs can completely remove global clocking. As a result, asynchronous designs may be more tolerant to timing variations. The ITRS also predicts that asynchrony will increase with the complexity of onchip systems. The power, design effort, and reliability cost of global clocks will also make increased asynchrony more attractive. Increasingly complex asynchronous systems or subsystems will thus become more prevalent in future VLSI systems. In order to fully realize the potential of asynchrony in an environment of variable supply voltage and latencies, system memories may need to be asynchronous together with the computation parts. In this paper, we concentrate on asynchronous SRAM. Our main contributions include: analysing the behaviour of latency in SRAM memory systems under different Vdds, developing asynchronous SRAM memory, and proposing a new method to build delay elements for bundled SRAM memory. We develop a fully Speed Independent (SI) [16] SRAM cell and a bundled SRAM bank technology by using such SI SRAM cells as delay elements. The remainder of the paper is organized as follows. Section 2 introduces existing asynchronous SRAM memory structures. Section 3 analyses the effects on the latency of the SRAM memory and its controller of different Vdds. Section 4 gives our asynchronous SRAM solutions and implementations, and proposes a new method to build SI delay elements for SRAM memory. Section 5 demonstrates a memory bank and the measurements in terms of latency, power consumption. Section 6 gives the conclusions and the future work. 2 Existing asynchronous SRAM memory Several asynchronous SRAM methods have been reported [5,6,7,8,9]. In [5] a methodology was mostly developed for designing and verifying low power asynchronous SRAM. An SI SRAM cell was alluded to in [5]. This memory cell is different from the conventional six transistor cell [15] and provides the possibility of checking that the data has been stored in memory. The paper however does not explain how the cell needs to be controlled nor does it include a controller design. [6,7,8,9] focus on asynchronous SRAM memory designs. [6] presents a four-phase handshake asynchronous SRAM design for self-timed systems. It proposes an SI circuit to realize completion detection of reading operations. However, the paper claims that completion detection is not suitable for writing operations. Because the critical circuit is the memory cell, it is said to be impractical to add a monitoring sensor to each memory cell to generate completion detection signals. Instead the paper proposes a delay based solution, which uses several delay lines for different delay regions as variation is considered. The other works [7,8,9] abandon SI altogether and adopt bun-
dled data methods based on delays. Noting that the delay of inverter chains commonly used in conventional SRAM to generate required timings for precharge and data access phase hardly match all the timing variations of the bit line activities across a wide range of supply voltages [11,12], the authors of [9] used a duplicated column of memory cells to replace inverter chains to serve as delay elements. Although in theory this offers potentially correct delay matching for memory under variable Vdd, so long as process variation [3] is kept under control, the method requires voltage references for precharge and sensing data. The voltage reference is assumed to be adjustable to accommodate the process, voltage, and temperature conditions. In summary, most of existing solutions work under worst case timing assumptions, and some of them also require adjustable and known reference voltages. However, in the energy harvesting environment, there may not be stable reference voltages in a system at all, so anything based on comparators will not work. All voltages in the system may be non-deterministic. All delays may therefore be non-deterministic. 3 Investigation on SRAM cells in terms of latency SRAM memory is constructed from SRAM sells, address decoders, precharge driver, write driver, read driver, and controller. Although there exist different structures of SRAM cells, here we only focus on the simplest 6T [15] cell which offers the best prospect for use in energy harvesting systems. Normally memory works based on timing assumption. However, energy harvesting systems work under a wide range of non-deterministic power. It is necessary to know how timing assumptions are affected under different Vdds. Here we investigate the difference between the latency on bit line drive and its corresponding typical inverter-chain delay elements used in controllers under different Vdds. This potential mismatch has already been pointed out in papers [11,12]. [11] concludes that the latency on inverter chains are getting worse and worse along with reducing the Vdd. [12] concludes that the percentage of the bit line drive time of the total access time under reducing Vdds is getting bigger and bigger. But do both types of delays increase at the same rate under the same Vdd reduction rate To emphasize the mismatch, we directly show the difference between the reading/writing times and the latency of delay elements in various Vdds in the right hand side of Figure 1. start SRAM finish Figure 1 Investigation on delay elements in various Vdd: Block diagram (left) and Results (right). The experiment bundles an SRAM cell with an inverter chain, with both operating under the same variable Vdd as shown in the left hand side of Figure 1. A start signal
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Page 5 and 6: that, one bit line will be discharg
Page 7 and 8: eturned to the initial states, Wa i
Page 9 and 10: Figure 8 shows the access time of t

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