Self-Timed SRAM for Energy Harvesting Systems - Electronics ...

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triggers reading/writing operation of the cell. This start signal is also connected to the inverter chain as its input signal. We measure the number of inverters the start signal has passed through when the reading/writing operation finishes. In reading, under lowest Vdd the memory is about 3 times slower than under the normal Vdd in terms of the number of inverters. In writing, under lowest Vdd the memory is about 2 times slower than under the normal Vdd in terms of the number of inverters. In other words, both reading from and writing to memory become slower at a much higher rate than inverter chains when Vdd is reduced, and inverter chain type delays do not track memory operation delays when both are under the same variable Vdd. This demonstrates that using standard inverter chains for memory delay bundling would require precise design-time delay characterization and conservative worst-case provisions which could be 2-3 times more wasteful for some cases. 4 Asynchronous SRAM solutions The characteristics of the energy harvesting systems lead to non-deterministic Vdd and delays across the entire system. To deal with this it is possible to employ asynchrony in the form of memory bundling or completion detection. For bundling, the above discussion has established that normal delay elements built using inverter chains are unsuitable for memory. A natural extension of using dummy SRAM cells as delay elements exists [9], but the method has too many assumptions and requirements such as known and variable reference voltages which may not be possible for energy harvesting systems. In this section, a fully Speed Independent (SI) SRAM memory is proposed. The SI circuits are not affected by delays on gates but delays on wires are assumed as zero or very little. This is generally not a problem for circuits of small size such as an individual 6T SRAM cell. However, fully SI solutions for memory banks can be expensive in terms of power and size of circuits and it also reduces performance [16]. A new method in which an asynchronous SRAM memory is bundled with SI SRAM serving as delay elements is proposed as a compromise. 4.1 Speed Independent SRAM WL Q Qb WE BL BLb WL Q Qb Db D BL BLb CDb (a) BL BLb CD (b) (c) Figure 2 Proposed SRAM cell (a) for SI solution, the write driver (b), and standard 6T cell (c). As discussed in [6], the reading completion detection can be built by monitoring the bit lines. For a 6T cell (Figure 2 (c)), in reading, the precharge pulls the two bit lines to high. Then the reading sets the WL high to open the two pass transistors. After
that, one bit line will be discharge to low. This means that the data is ready for reading. However, the writing operation is to write each bit of data to its corresponding cell. It is impractical to monitor all cells. Instead, we still monitor the bit lines. Figure 2 (a) shows our proposed SI SRAM cell. The cell is based on the normal 6T cell. The new cell duplicates the bit lines and uses the six extra transistors to control the two discharge channels. The cell works as follows. The reading operation is the same as the normal 6T cell. The writing operation is arranged as: 1) precharging the four bit lines to high; 2) enabling the writing data on BL and BLb; 3) setting the WL high to write the data into cell; 4) monitoring the CD and CDb; 5) when one of them changes to low, writing done. The writing driver is shown in Figure 2 (b). After the writing driver is enabled, one of BL and BLb is low and the other is floating. If the new data is the same as the data stored in the cell, for example D=1, CD will be discharged (Qb goes to CD). If the new data and the stored data are not the same, for example, Q=1 and D=0, BL is low and then waiting for Qb high to discharge CDb. In this situation, BL is low and written to Q. But only after the Q is propagated to Qb, the discharging path is opened. In fact, this method introduces a reading at the writing operation with the execution order “precharging, writing, reading”. However, unlike the normal reading operation, it uses the duplicated bit lines as a reading port and to guarantee the writing data being stored into the cell. The two discharge paths can be taken as two AND gates implemented in transmission gate logic. We optimize this method based on ideas borrowed from [14]. By changing the execution order to “precharging, reading, writing”, the duplicated bit lines in Figure 2 (a) can be removed. The normal 6T SRAM cell in Figure 2 (c) can be used instead with considerable savings. SRAM cells depend on control signals. The control signals PreCharge, WL, and WE, are issued based on timing assumptions in existing asynchronous SRAMs. An intelligent controller is designed to manage these control signals based on the new execution order. To completely remove timing assumption, Delay Insensitive (DI) circuits are the best choice. However, DI circuits are limited in practice [2]. Instead, SI circuits suffice here. The block diagram of the controller is shown in Figure 3. Wa Wr Rr Ra Controller Pre Dn WL Dn WE Dn Data Memory Figure 3 Block diagram of the controller. There are two handshake protocols ((Wr,Wa) and (Rr,Ra)) to connect with the processing unit and three protocols ((Pre,Dn), (WL,Dn), and (WE,Dn)) with the memory system. The signals (Wr,Wa) are the writing request and its finish signals. The (Rr,Ra) pair is the reading request and its finish signals. The (Pre,Dn) handshake is the precharge request and its done signals. The STG specifications of the reading and writing operation are shown in Figure 4.
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Page 9 and 10: Figure 8 shows the access time of t

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