Self-Timed SRAM for Energy Harvesting Systems - Electronics ...

Figure 8 shows the access time of the SRAM. The access time is the latency from
the reading/writing request to the done signal. For example, under 1V, the worst access
time for writing and reading are 5.4ns and 3.0ns. And under 190mV, they are
1.6µs and 4.0µs respectively.
6 Conclusions and future work
In this paper, we focus on SRAM memory design for energy harvesting systems.
Normally, this kind of system works under a variable power supply with high power
efficiency and not just low power. Under such non-deterministic power supply assumption,
existing asynchronous SRAM working based on bundled delay has huge
penalties and is impractical because a need for voltage references.
The latency difference between SRAM memory and its controller under different
Vdds is investigated. With reducing Vdd, the latency mismatch becomes bigger and
bigger if traditional inverter chain delays are used. Under 190mV, the mismatch is
more than twice bigger than under the normal 1V Vdd in 90nm technology.
An SI SRAM is proposed and designed. The SRAM has a simple interface, which
is similar to the normal SRAM including data, address, reading request, reading acknowledgement,
writing request, and writing acknowledgement. The internal signals
for memory control are fully triggered by the corresponding events of the memory
systems. This works by monitoring the bit lines of memory.
A new method is proposed to implement SI writing operation based on ideas from
[14]. This solves the previously considered impractical or impossible problem of
completion detection for writing operations.
A 1Kb (64X16) SI SRAM is implemented using Cadence toolkits. The simulation
results show the SRAM working as expected from 190mV to 1V. Meanwhile, the
energy consumption and the worst case performance are measured. The measurements
show the SRAM cell has acceptable characteristics.
However, as the completion detection logic in SI SRAM is expensive in terms of
area, performance, and power. A compromised SRAM is designed as well based on
the modified SI SRAM.
The new SRAM is based on the bundled delay principle. However unlike existing
asynchronous SRAM solutions, a column (the worst column, if it can be identified) of
SI SRAM cells doubles as delay elements. This column should be slower anyway than
the other columns because completion detection elements take extra time. The other
columns of the memory cells are bundled with this column.
However, so far, we have only investigated basic asynchronous SRAM design.
Other issues, such as static noise margin, readability, stability, etc. need further study.
These are the targets of our future research. We will also investigate multi-port asynchronous
SRAM in the context of variable and nondeterministic Vdd.
Acknowledgement
This work is supported by the EPSRC project Holistic (EP/G066728/1) at Newcastle
University. During the work, we get very helpful discussions from our colleagues, Dr
Alex Bystrov and other members of the MSD research group. The authors would like
to express our thanks to them.