XAPP112: Designing With XC9500XL CPLDs - App Note, V1.1 (01/99)

R
Designing With XC9500XL CPLDs
t F
t IN
t GCK
t GSR
t LOGILP
t LOGI
S*t PTA
D/T
t PDI
Q
t SLEW
t OUT
t SUI t COI
t
t HI
PTCK
EC t AOI
t
> t ECHO
t RAI
EN
t PTSR
t
SR
ECSUI
t PTTS
Macrocell
t GTS
Figure 8: XC9500XL Timing Model
Table 3: Timing Parameters
Parameter
t AOI
t COI
t E
t ECHO
t ECSUI
t GCK
t GSR
t GTS
t HI
t IN
t LOGI
t LOGILP
t OU
t PDI
t PTA
t PTC
t PTTS
t RAI
t SLEW
t SUI
Practical Considerations
Power On Model
Name
Register asynchronous S/R to output delay
Resister clock to output valid delay
Output tri-state enable time
Enable clock hold time
Enable clock setup time
GCK buffer delay
GSR buffer delay
GTS buffer delay
Register hold time
Input buffer delay
Internal logic delay
Internal low power logic delay
Output buffer time delay
Combinatorial logic propagation delay
Incremental product term allocator delay
Product term clock delay
Product term tri-state delay
Register asynchronous S/R recovery before clock
Slew rate limited delay
Register setup time
XC9500XL parts are designed to provide a flexible voltage
environment for today’s demanding voltage environments.
Key to this is considering lots of details that permit designers
the choice of speeds and densities, but automatically
handle electrical issues that are frequently overlooked by
others. First on the list is a flexible “Power On Model”.
Figure 9 shows how an XC9500XL powers up. In this diagram,
we will assume V CCINT and V CCIO are either tied
together or rising together. In this case, as V CC rises, the
pins are assumed initially to be in high impedance condition,
with large pullup resistance to V CCINT . This provides a
logic high that can be easily counter driven by a pin from an
external chip wishing to dominate that electrical point. At
one point in the power up process, the XC9500XL passes
its internal configuration bits to the parts functional
resources and the outputs are configured as dictated by the
programming pattern. When the part is powered down,
small keeper circuits retain the last value the pins drove as
VCC drops. Some variation occurs if V CCIO is cycled separately,
but in all cases, the most benign electrical state is
assumed.
Outputs as configured
Outputs HIGHZ, pulled up
First time power up
Figure 9: Power Up Model
Outputs follow
last value (assuming
V CCIO is still up here)
6 XAPP112 January 22, 1999 (Version 1.1)