Micron ® PISMO ™ Module Data Sheet
Micron ® PISMO ™ Module Data Sheet
Micron ® PISMO ™ Module Data Sheet
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PDF: 09005aef827fda9b/Source: 09005aef827fda71 <strong>Micron</strong> Technology, Inc., reserves the right to change products or specifications without notice.<br />
<strong>PISMO</strong>2_00001_datasheet.fm - Rev. B 11/07 EN 19 ©2007 <strong>Micron</strong> Technology, Inc. All rights reserved.<br />
Figure 10: NAND Flash Interface Schematic<br />
5<br />
5<br />
NA_1V8<br />
4<br />
4<br />
3<br />
100n 100n 100n<br />
100n 100n 100n<br />
100n 100n 100n 100n 100n 100n<br />
D D<br />
U10<br />
NA_IO[0..15]<br />
NA_IO[0..15]<br />
C<br />
NA_CS0_N<br />
NAND_WP<br />
NA_RY0<br />
NA_CLE<br />
NA_ALE<br />
NA_RE_N<br />
NA_WE_N<br />
LCK<br />
NA_IO0<br />
NA_IO1<br />
NA_IO2<br />
NA_IO3<br />
NA_IO4<br />
NA_IO5<br />
NA_IO6<br />
NA_IO7<br />
NA_IO[0..15]<br />
NA_IO[0..15]<br />
NA_CS0_N<br />
NAND_WP<br />
NA_RY0<br />
NA_CLE<br />
NA_ALE<br />
NA_RE_N<br />
NA_WE_N<br />
LCK<br />
C6<br />
C3<br />
C8<br />
D5<br />
C4<br />
D4<br />
C7<br />
G5<br />
CE<br />
WP<br />
R/B<br />
CLE<br />
ALE<br />
RE<br />
WE<br />
LOCK<br />
NA_IO0<br />
NA_IO1<br />
NA_IO2<br />
NA_IO3<br />
NA_IO4<br />
NA_IO5<br />
NA_IO6<br />
NA_IO7<br />
NA_IO8<br />
NA_IO9<br />
NA_IO10<br />
NA_IO11<br />
NA_IO12<br />
NA_IO13<br />
NA_IO14<br />
NA_IO15<br />
C<br />
A1<br />
B9<br />
B10<br />
D3<br />
D6<br />
E3<br />
E4<br />
E5<br />
NC_0<br />
NC_5<br />
NC_6<br />
NC_7<br />
NC_8<br />
NC_11<br />
NC_12<br />
NC_13<br />
NC_24<br />
NA_1V8<br />
MT29F1G16AB<br />
B B<br />
G4<br />
NC_23 G3<br />
B1<br />
NC_4<br />
NC_21<br />
NC_22<br />
F7<br />
F8<br />
NC_3<br />
A10 NC_2<br />
A9 NC_1<br />
I/O7<br />
A2<br />
G7<br />
I/O5<br />
I/O6<br />
J7<br />
G6<br />
I/O4 K6<br />
E8<br />
NC_16<br />
NC_15<br />
I/O2<br />
I/O3<br />
J5<br />
D7<br />
D8<br />
E6<br />
E7<br />
NC_9<br />
NC_10<br />
NC_14<br />
K4<br />
I/O1 H4<br />
I/O0<br />
I/O8<br />
J3<br />
NC_17<br />
NC_18<br />
NC_19<br />
NC_20<br />
F3<br />
F4<br />
F5<br />
F6<br />
H3<br />
I/O9<br />
I/O10<br />
J4<br />
H5<br />
I/O11 K5<br />
I/O12 H6<br />
I/O13 K7<br />
I/O14 H7<br />
I/O15<br />
J8<br />
NC_26 G8<br />
NC_27<br />
NC_28<br />
NC_29<br />
NC_30<br />
NC_31<br />
L1<br />
L2<br />
L9<br />
L10<br />
M1<br />
NC_32 M2<br />
NC_33 M9<br />
NC_34 M10<br />
U11<br />
I/O0<br />
MT29F1G08AB<br />
R23<br />
1k<br />
H4<br />
I/O1<br />
I/O2<br />
J4<br />
K4<br />
I/O3 K5<br />
I/O4 K6<br />
I/O5<br />
I/O6<br />
J7<br />
K7<br />
I/O7<br />
J8<br />
NC_27 G8<br />
NC_28 H3<br />
NC_29 H5<br />
NC_30 H6<br />
NC_31 H7<br />
F4<br />
F5<br />
F6<br />
NC_18<br />
NC_19<br />
NC_20<br />
NC_21<br />
NC_22<br />
NC_23<br />
NC_32<br />
NC_33<br />
F7<br />
F8<br />
J3<br />
J5<br />
G3<br />
NC_24 G4<br />
NC_25 G6<br />
NC_26 G7<br />
NC_34<br />
NC_35<br />
NC_36<br />
NC_37<br />
NC_38<br />
L1<br />
L2<br />
L9<br />
L10<br />
M1<br />
NC_39 M2<br />
NC_40 M9<br />
NC_41 M10<br />
C6<br />
C3<br />
C8<br />
D5<br />
C4<br />
D4<br />
C7<br />
G5<br />
CE<br />
WP<br />
R/B<br />
CLE<br />
ALE<br />
RE<br />
WE<br />
LOCK<br />
A1<br />
A2<br />
A9<br />
A10<br />
B1<br />
B9<br />
B10<br />
D3<br />
D6<br />
D7<br />
D8<br />
E3<br />
E4<br />
E5<br />
E6<br />
E7<br />
E8<br />
F3<br />
NC_0<br />
NC_1<br />
NC_2<br />
NC_3<br />
NC_4<br />
NC_5<br />
NC_6<br />
NC_7<br />
NC_8<br />
NC_9<br />
NC_10<br />
NC_11<br />
NC_12<br />
NC_13<br />
NC_14<br />
NC_15<br />
NC_16<br />
NC_17<br />
J5<br />
HE-142 1<br />
2<br />
Place on the<br />
top side<br />
C44<br />
LCK<br />
C43<br />
Package 0306 Package 0306<br />
C45 C46 C47 C48<br />
C38 C37 C39 C40<br />
NA_1V8<br />
NA_1V8<br />
R15<br />
NA_LCK<br />
NA_CS0_N<br />
NA_LCK<br />
NA_CS0_N<br />
R22 0<br />
DNI<br />
1k<br />
NA_RY0<br />
NA_CLE<br />
NA_CLE<br />
NA_RY0<br />
<strong>Micron</strong> Technology<br />
Systems Engineering<br />
NA_ALE<br />
NA_ALE<br />
via A. Pacinotti, 7<br />
67051, Avezzano<br />
A<br />
NA_RE_N<br />
NA_WE_N<br />
NA_RE_N<br />
NA_WE_N<br />
R16<br />
DNI<br />
1k<br />
Title<br />
ITALY<br />
A<br />
NA_WP_N<br />
NA_WP_N<br />
R18 0<br />
NAND_WP<br />
NAND<br />
R17<br />
DNI<br />
D o c u m e n t N u m b e r<br />
M I C R O N - P I S M O 2 - 0 0 0 0 1<br />
R e v i s i o n<br />
4 . 0<br />
Size<br />
A-3<br />
1k<br />
Vcc_1<br />
J6<br />
Vcc_2 H8<br />
FLASH NAND x8 - BGA<br />
Vss_1<br />
Vss_2<br />
Vss_3<br />
K8<br />
C5<br />
K3<br />
3<br />
NA_1V8<br />
2<br />
2<br />
NA_1V8<br />
Vcc_2 H8<br />
Vcc_1<br />
J6<br />
1.8V NAND x16 - BGA<br />
Vss_1<br />
Vss_2<br />
Vss_3<br />
K8<br />
C5<br />
K3<br />
C41<br />
C42<br />
CONFIDENTIAL AND PROPRIETARY INFORMATION<br />
The information contained herein is proprietary of <strong>Micron</strong> Technology. Any reproduction, in whole or in part,<br />
disclosure, or use of this drawing is expressly prohibited except as specified in writing by <strong>Micron</strong> Technology.<br />
Date: Tuesday, April 03, 2007<br />
<strong>Sheet</strong> 5 of 6<br />
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1<br />
<strong>PISMO</strong>2-00001: <strong>Micron</strong> Mobile DDR SDRAM + NAND <strong>Module</strong><br />
Mechanical Specifications<br />
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