Chapter 4: The Instruction Set Architecture - 10/31/2013 02:13:31 ...

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4-10 An Example From Data Bus Datapath Register Source 1 (rs1) Chapter 4: The Instruction Set Architecture Register Source 2 (rs2) Register File Control Unit selects registers and ALU function To Address Bus ALU To Data Bus Status to Control Unit Register Destination (rd) • The ARC datapath is made up of a collection of registers known as the register file and the arithmetic and logic unit (ALU). Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
4-11 The ARC ISA • The ARC ISA is a subset of the SPARC ISA. Chapter 4: The Instruction Set Architecture Memory Logic Arithmetic Control Mnemonic Meaning ld Load a register from memory st Store a register into memory sethi Load the 22 most significant bits of a register andcc Bitwise logical AND orcc Bitwise logical OR orncc Bitwise logical NOR srl Shift right (logical) addcc Add call Call subroutine jmpl Jump and link (return from subroutine call) be Branch if equal bneg Branch if negative bcs Branch on carry bvs Branch on overflow ba Branch always Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Page 1 and 2: 4-1 Chapter 4: The Instruction Set
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Page 15 and 16: 4-15 Signed Integer Byte Signed For
Page 27 and 28: 4-27 0 0 Chapter 4: The Instruction
Page 29 and 30: 4-29 Input and Output for the ISA A
Page 33 and 34: 4-33 // This is file add.java Chapt

Chapter 4: The Instruction Set Architecture - 10/31/2013 02:13:31 ...

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