Chapter 4: The Instruction Set Architecture - 10/31/2013 02:13:31 ...
Chapter 4: The Instruction Set Architecture - 10/31/2013 02:13:31 ...
Chapter 4: The Instruction Set Architecture - 10/31/2013 02:13:31 ...
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4-14<br />
<strong>Chapter</strong> 4: <strong>The</strong> <strong>Instruction</strong> <strong>Set</strong> <strong>Architecture</strong><br />
ARC <strong>Instruction</strong> and PSR Formats<br />
op<br />
SETHI Format<br />
<strong>31</strong> 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 <strong>13</strong> 12 11 <strong>10</strong> 09 08 07 06 05 04 03 <strong>02</strong> 01 00<br />
0 0 rd op2<br />
imm22<br />
Branch Format<br />
0 0<br />
0 cond<br />
op2<br />
disp22<br />
<strong>31</strong> 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 <strong>13</strong> 12 11 <strong>10</strong> 09 08 07 06 05 04 03 <strong>02</strong> 01 00<br />
CALL format<br />
0 1<br />
disp30<br />
i<br />
<strong>31</strong> 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 <strong>13</strong> 12 11 <strong>10</strong> 09 08 07 06 05 04 03 <strong>02</strong> 01 00<br />
Arithmetic<br />
Formats<br />
1 0 rd op3<br />
1 0 rd op3<br />
rs1<br />
rs1<br />
0<br />
1<br />
0 0 0 0 0 0 0 0 rs2<br />
simm<strong>13</strong><br />
<strong>31</strong> 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 <strong>13</strong> 12 11 <strong>10</strong> 09 08 07 06 05 04 03 <strong>02</strong> 01 00<br />
1 1 rd op3<br />
rs1<br />
0<br />
0 0 0 0 0 0 0 0 rs2<br />
Memory Formats<br />
1 1 rd op3<br />
rs1<br />
1<br />
simm<strong>13</strong><br />
op<br />
Format<br />
op2<br />
Inst.<br />
op3 (op=<strong>10</strong>)<br />
op3 (op=11)<br />
cond<br />
branch<br />
00<br />
01<br />
<strong>10</strong><br />
11<br />
SETHI/Branch<br />
CALL<br />
Arithmetic<br />
Memory<br />
0<strong>10</strong><br />
<strong>10</strong>0<br />
branch<br />
sethi<br />
0<strong>10</strong>000<br />
0<strong>10</strong>001<br />
0<strong>10</strong>0<strong>10</strong><br />
0<strong>10</strong>1<strong>10</strong><br />
<strong>10</strong>01<strong>10</strong><br />
11<strong>10</strong>00<br />
addcc<br />
andcc<br />
orcc<br />
orncc<br />
srl<br />
jmpl<br />
000000<br />
000<strong>10</strong>0<br />
ld<br />
st<br />
0001<br />
0<strong>10</strong>1<br />
01<strong>10</strong><br />
0111<br />
<strong>10</strong>00<br />
be<br />
bcs<br />
bneg<br />
bvs<br />
ba<br />
PSR<br />
<strong>31</strong> 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 <strong>13</strong> 12 11 <strong>10</strong> 09 08 07 06 05 04 03 <strong>02</strong> 01 00<br />
n z v c<br />
Principles of Computer <strong>Architecture</strong> by M. Murdocca and V. Heuring<br />
© 1999 M. Murdocca and V. Heuring
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