Chapter 4: The Instruction Set Architecture - 10/31/2013 02:13:31 ...

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4-20 Chapter 4: The Instruction Set Architecture One, Two, Three-Address Machines • Two Address Instructions: In a two-address instruction, one of the operands is overwritten by the result. Here, the code for the expression A = B*C + D is: load mult add B, A C, A D, A The program size is now 3×(1+2×2) or 15 bytes. Memory traffic is 15 + 2×2 + 2×2×3 or 31 bytes. Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
4-21 Chapter 4: The Instruction Set Architecture One, Two, Three-Address Machines • One Address (Accumulator) Instructions: A one-address instruction employs a single arithmetic register in the CPU, known as the accumulator. The code for the expression A = B*C + D is now: load B mult C add D store A The load instruction loads B into the accumulator, mult multiplies C by the accumulator and stores the result in the accumulator, and add does the corresponding addition. The store instruction stores the accumulator in A. The program size is now 2×2×4 or 16 bytes, and memory traffic is 16 + 4×2 or 24 bytes. Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring
Page 1 and 2: 4-1 Chapter 4: The Instruction Set
Page 11 and 12: 4-11 The ARC ISA • The ARC ISA is
Page 15 and 16: 4-15 Signed Integer Byte Signed For
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Page 27 and 28: 4-27 0 0 Chapter 4: The Instruction
Page 29 and 30: 4-29 Input and Output for the ISA A
Page 33 and 34: 4-33 // This is file add.java Chapt

Chapter 4: The Instruction Set Architecture - 10/31/2013 02:13:31 ...

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