Chapter 4: The Instruction Set Architecture - 10/31/2013 02:13:31 ...
Chapter 4: The Instruction Set Architecture - 10/31/2013 02:13:31 ...
Chapter 4: The Instruction Set Architecture - 10/31/2013 02:13:31 ...
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4-21<br />
<strong>Chapter</strong> 4: <strong>The</strong> <strong>Instruction</strong> <strong>Set</strong> <strong>Architecture</strong><br />
One, Two, Three-Address Machines<br />
• One Address (Accumulator) <strong>Instruction</strong>s: A one-address instruction<br />
employs a single arithmetic register in the CPU, known as the<br />
accumulator. <strong>The</strong> code for the expression A = B*C + D is now:<br />
load B<br />
mult C<br />
add D<br />
store A<br />
<strong>The</strong> load instruction loads B into the accumulator, mult multiplies<br />
C by the accumulator and stores the result in the accumulator,<br />
and add does the corresponding addition. <strong>The</strong> store instruction<br />
stores the accumulator in A. <strong>The</strong> program size is now<br />
2×2×4 or 16 bytes, and memory traffic is 16 + 4×2 or 24 bytes.<br />
Principles of Computer <strong>Architecture</strong> by M. Murdocca and V. Heuring<br />
© 1999 M. Murdocca and V. Heuring
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