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VR Series Microprocessors
NEC Electronics Inc.
Low-Latency Instructions
The MIPS IV instruction set supports four multiply-addsubtract
instructions:
• Multiply-Add (MADD)
• Multiply-Subtract (MSUB)
• Negative Multiply-Add (NMADD)
• Negative Multiply-Subtract (NMSUB)
Two separate floating-point computations can be performed
with one instruction.
Large On-Chip Primary Caches
The VR5000 contains separate 32 KB data and instruction
caches. Each cache has a 32-byte fixed line size and is twoway
set associative, which helps to increase the hit rate over a
direct-mapped implementation. Cache lines may be classified
as write-through or write-back on a per-page basis.
Both caches are virtually indexed and physically tagged. A
virtually indexed cache allows the cache access to begin as
soon as the virtual address is generated, as opposed to waiting
for the virtual-to-physical translation. The cache is accessed at
the same time as the address translation is performed.
Having large primary caches allows more of the application to
be executed on chip, reducing accesses to slower secondary
caches and main memory. This in turn reduces bus utilization
and allows the application to run faster, since fewer off-chip
accesses are required.
Contact List
USA
VR Series RISC Products Group
NEC Electronics Inc.
2880 Scott Boulevard
Santa Clara, CA 95050
Tel: (800) 366-9782 or (408) 588-6000
E-mail: vrsupport@el.nec.com
Japan
NEC Corporation
1753 Shimonumabe, Nakahara-Ku
Kawasaki, Kanagawa 211, Japan
Tel: +81-44-435-1485
Secondary Cache Support
Large applications often use a secondary cache to reduce the
number of accesses to slower main memory. The VR5000
contains a dedicated secondary cache interface with a
complete set of signals (such as data enable, chip enable,
output enable, address match, cache valid, line index, and
word index) that provides an efficient interface with the
processor, a secondary cache configured as 512 KB or 1 MB
or 2 MB, and secondary cache tag RAM.
The secondary cache interface supports multiple cache sizes
and the write-through data transfer protocol. Data transfers to
the secondary cache share the 64-bit system bus. Uncached
bus cycles are not evaluated by the secondary cache control
logic as they travel to the external agent. Uncached operations
such as video screen updates can be passed directly to the
system logic responsible for routing the data to the screen
without any delays from the secondary cache logic.
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