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Chipsets
NEC Electronics Inc.
VRC4372
I/O Controller for the
VR43xx Family
NEC Electronics Inc.
Salient Features
PCI arbitration for six external and one internal
PCI masters
Timer and beeper source
ISA-like I/O bus
Four independent DMA channels
Ten chip selects
N-to-3 interrupt controller
Interrupts generated from 14 input pins and two
internal timers
Test port to place chip in scan mode
3.3-volt compliant and 5-volt tolerant
33 MHz bus frequency
CPUs Supported
NEC VR43xx
Product Overview
The VRC4372 is a PCI-based I/O controller for a
high-performance, low-cost system implementation based on
the VR43xx microprocessor. The VRC4372 contains the
functional blocks described below.
PCI Bus Interface Controller
• Compliance with 3.3-volt PCI interface standards (version
2.1)
• 5-volt PCI signaling in a controlled environment (with
voltage spikes less than 7.6 volts and DC levels less than
6.6 volts)
• PCI bus arbitration for six external and one internal PCI
masters
I/O Controller
• 16-bit ISA-like I/O bus and four independent DMA
channels
• Chip-select and control signals for interfacing to external
peripheral chips
• N-to-3 interrupt controller (interrupts from the keyboard
and mouse, 14 input pins, two internal timers, and four
DMA channels can be encoded onto one of three outgoing
interrupt lines)
• Four programmable DMA channels
— Unique TCn, EOP, DREQ, and DACKn signals on
each channel
— Block or single transfers
— Read or write requests
— I/O-device-demanded service requests via DREQx
— Software-initiated requests
— Channel suspend via the MASKn register bit
— I/O device transfer termination via EOP
— Channel reload notification and termination
notification via an interrupt
— Efficient PCI bus data packing mode
— Byte/short scattering/gathering capabilities (one per
PCI word)
Each channel has registers and status bits associated with its
control and operation. A current address and current count
register pair are used to address the current DMA buffer in
PCI memory space. A reload start and reload count register
pair provide a reload mechanism through which channel
chaining can be accomplished. Fifth and sixth registers
provide the channel with mode and status control.
A global control register specifies global DMA attributes such
as arbitration scheme selection.
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