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Chipsets
Algorithmics Ltd.
BONITO
MIPS System
Controller Cores
and Chips
Algorithmics Ltd.
Salient Features
Decent clock rates: the ASIC is very
conservatively targeted at 83 MHz, but we
expect to see higher frequencies
Reliable BGA packages: we know production
engineers hate big QFPs, and we thought that insystem
price/performance would get worse if we
were short of pins
Unique debug mode/port: there is a mode that
makes all cycles visible to a probe board
connected to the SDRAM interface, so that
developers can easily watch addresses and data
without loading the board with a special
connector
Core logic is synthesizable Verilog: the same
source code is used to produce both a Xilinx
FPGA implementation (using “Synplicity”) and
an ASIC (using Synopsys tools). Core logic
users also get a test-bench using realistic models
of connected devices. It’s all Algorithmicswritten
or freely redistributable code.
Supports variant MIPS CPUs: not all MIPS
CPUs sharing the SysAD bus are the same, but
BONITO supports all known 32-bit variants
Programmer and development support: basic
source code and a full bug list are freely
available on line
Configurable SDRAM port: runs synchronous to
the CPU. Glueless for small systems, supporting
64-bit DIMMs. Accepts external isolating
switches and/or registers/drivers for larger
configurations.
PCI 2.1, 33 MHz, 32 bits: basic PCI as is widely
used throughout the industry. Suitable for “host”
or “peripheral” applications. The PCI clock need
not be related to the CPU clock.
I/O buffer cache: provides efficient PCI master
access to local memory (usually the key I/O
performance characteristic)
High integration: glueless support for MIPS
CPU reset (including the infamous
“configuration bitstream”), for example
algorithmics
CPUs Supported
All NEC VR Series processors
Product Overview
BONITO is a MIPS system controller that connects one of
many different MIPS CPUs to a local SDRAM memory
system, a PCI expansion bus, and a simple local I/O bus for
ROM and 8-bit peripherals. BONITO is available now as
reusable Verilog code configurable between 64-bit and 32-bit
bus width at the CPU/SDRAM port. An ASIC for 32-bit
systems is available now.
Why BONITO?
There are already several MIPS system controllers out there.
BONITO is a cost-effective solution that will get you to
market faster with a higher quality product.
• Algorithmics’ MIPS system design experience goes back
more than ten years
• Appropriate detailing: we included, for example, a PCI
arbiter and interrupt controller; we omitted, for example, a
UART, or fast/wide PCI. Why? see below.
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