Download - Toppy.org.uk

Chipsets
Algorithmics Ltd.
implementation and (using Synopsys tools) into an ASIC. The
code is modular, though the division is not conventional - we
observed that making a strict separation between the CPU
interface and the SDRAM controller, for instance, leads to
extra CPU cache refill latency and lower performance.
Along with the chip design we have a large test harness
consisting of bus models of the devices to which BONITO
attaches. The MIPS “CPU” bus model reads test scripts that
exercise the virtual system, providing extensive test coverage
even of difficult design points.
Algorithmics wrote all the synthesisable code, though the test
harness does use a few freely redistributable files from other
authors (special thanks to Micron for its SDRAM DIMM
model, for instance). We will be very flexible about licensing.
Contact List
England
Algorithmics Ltd.
19 Church Road
Teversham
Cambs CB1 5AW, England
Tel: +44 20 7700 3301
Fax: +44 20 7700 3384
E-mail: wsde@algor.co.uk
Internet: http://www.algor.co.uk
28