TigerSHARC DSP Hardware Specification, Revision 1.0.2, Link Ports

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Transmission DelaysAn example of a token switch regret is shown in Figure 8-9 on page 8-15.In this example:1. After the transmitter has set LxCLKOUT high, the receiver identifiesthis as token switch enable and requests the token switch.2. The receiver’s request is too late to guarantee the token switch andthe transmitter signals a regret by setting LxCLKOUT low. Thereceiver identifies this and goes back to being a receiver. Thereceiver indicates that it is ready to receive more data by ackowledging.The transmitter starts transmitting again.3. The LxDIR pin of the transmitter changes to low when it enablesthe token switch. The transmitter sets it LxDIR back to high onlywhen the transmitter starts to transmit data again. The receiverdoes not set its LxDIR output high because it never gets to the pointof transmitting data.Transmission DelaysThe links should be able to function even if there are delays between thesource and destination. The delays of the different link signals (LxCLK andLxDAT) are matched to tolerances specified in the data sheet.The data sampled at the receiver uses the input LxCLK, so the delay has noeffect. Complications can arise, however, when token switches areinvolved. The maximum delay can be derived from information providedin the Data Sheet.8 - 16 TigerSHARC DSP Hardware Specification
Link Portsdata are transmitted by Adata are transmitted by BTiming at ALxCLKOUTLxCLKINtransmission delayLxDAT [7:0]a14a15b0b1b2Lx DIR (A)Timing at BLxCLKINLxCLKOUTLxDAT [7:0]a12a13a14a15b0 b1 b2 b3LxDIR (B)Figure 8-10. Token Switch from A to B with DelayFigure 8-10 shows the effect of the delay between two TigerSHARC®DSPs. The transmitter (TigerSHARC® DSP A) sets LxCLKOUT high toindicate a token switch enable. The receiver (TigerSHARC® DSP B)TigerSHARC DSP Hardware Specification 8 - 17
Page 1 and 2: 8 LINK PORTSFigure 8-0.Table 8-0.Li
Page 4 and 5: Link Architecturefrom the shift reg
Page 7 and 8: Link PortsThe interrupt can be used
Page 11 and 12: Link Ports3. One cycle after the tr
Page 14 and 15: Link Port Communication ProtocolThe
Page 18 and 19: Error Detection Mechanismssenses th
Page 20 and 21: Control Register (LCTLx)The checksu
Page 22 and 23: Control Register (LCTLx)Table 8-3.
Page 24: Status Register (LSTATx)Table 8-4.

TigerSHARC DSP Hardware Specification, Revision 1.0.2, Link Ports

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