ADSP-219x/2191 DSP Hardware Reference, Introduction

1 INTRODUCTIONFigure 1-0.Table 1-0.Listing 1-0.PurposeThe ADSP-219x/2191 DSP Hardware Reference provides architecturalinformation on the ADSP-219x modified Harvard architecture DigitalSignal Processor (DSP) core and ADSP-2191 DSP product. The architecturaldescriptions cover functional blocks, buses, and ports, including allthe features and processes they support. For programming information,see the ADSP-219x DSP Instruction Set Reference.AudienceDSP system designers and programmers who are familiar with signal processingconcepts are the primary audience for this manual. This manualassumes that the audience has a working knowledge of microcomputertechnology and DSP-related mathematics.DSP system designers and programmers who are unfamiliar with signalprocessing can use this manual, but should supplement this manual withother texts, describing DSP techniques.All readers, particularly system designers, should refer to the DSP’s datasheet for timing, electrical, and package specifications. For additional suggestedreading, see “For more Information about Analog Products” onpage 1-31.ADSP-219x/2191 DSP Hardware Reference 1-1

Overview—Why Fixed-Point DSP?Overview—Why Fixed-Point DSP?A digital signal processor’s data format determines its ability to handle signalsof differing precision, dynamic range, and signal-to-noise ratios.Because 16-bit, fixed-point DSP math is required for certain DSP codingalgorithms, using a 16-bit, fixed-point DSP can provide all the featuresneeded for certain algorithm and software development efforts. Also, anarrower bus width (16-bit as opposed to 32- or 64-bit wide) leads toreduced power consumption and other design savings. The extent towhich this is true depends on the fixed-point processor’s architecture.High-level language programmability, large address spaces, and widedynamic range allow system development time to be spent on algorithmsand signal processing concerns, rather than assembly language coding,code paging, and error handling. The ADSP-2191 DSP is a highly integrated,16-bit fixed-point DSP that provides many of these designadvantages.ADSP-219x Design AdvantagesThe ADSP-219x family DSPs are high-performance 16-bit DSPs for communications,instrumentation, industrial/control, voice/speech, medical,military, and other applications. These DSPs provide a DSP core that iscompatible with previous ADSP-2100 family DSPs, but provides manyadditional features. The ADSP-219x core combines with on-chip peripheralsto form a complete system-on-a-chip. The off-core peripherals addon-chip SRAM, integrated I/O peripherals, timer, and interruptcontroller.The ADSP-219x architecture balances a high performance processor corewith high performance buses (PM, DM, DMA). In the core, every computationalinstruction can execute in a single cycle. The buses andinstruction cache provide rapid, unimpeded data flow to the core to maintainthe execution rate.1-2 ADSP-219x/2191 DSP Hardware Reference

IntroductionFigure 1-1 shows a detailed block diagram of the processor, illustrating thefollowing architectural features:• Computation units—multiplier, ALU, shifter, and data register file• Program sequencer with related instruction cache, interval timer,and Data Address Generators (DAG1 and DAG2)• Dual-blocked SRAM• External ports for interfacing to off-chip memory, peripherals, andhosts• Input/Output (I/O) processor with integrated DMA controllers,serial ports (SPORTs), serial peripheral interface (SPI) ports, and aUART port• JTAG Test Access Port for board test and emulationFigure 1-1 also shows the three on-chip buses of the ADSP-219x: the ProgramMemory (PM) bus, Data Memory (DM) bus, and Direct MemoryAccessing (DMA) bus. The PM bus provides access to either instructionsor data. During a single cycle, these buses let the processor access two dataoperands (one from PM and one from DM), and access an instruction(from the cache).The buses connect to the ADSP-219x’s external port, which provides theprocessor’s interface to external memory, I/O memory-mapped, and bootmemory. The external port performs bus arbitration and supplies controlsignals to shared, global memory and I/O devices.ADSP-219x/2191 DSP Hardware Reference 1-3

ADSP-219x Design AdvantagesADSP-219xDSP COREINTERRUPT CONTROLLER/TIMERS/FLAGSCACHE64× 24-BITINTERNAL SRAMTWO INDEPENDENT BLOCKSADDRESSDATAADDRESSDATAB L O C K 0B L O C K 1JTAGTEST &EMULATION6DAG14 × 4 × 16DAG24 × 4 × 16PM ADDRESS BUSDM ADDRESS BUSPROGRAMSEQUENCER242424DMAADDRESS24DMADATAEXTERNALPORTADDR BUSMUX22BUSCONNECT(PX)PM DATA BUSDM DATA BUS2416EXTERNAL MEMORYINTERFACEDATA BUSMUX16DATAREGISTERFILEINPUTREGISTERSRESULTREGISTERSMULT16×16-BITBARRELSHIFTERALUCOREINTERFACEI/O REGISTERS(MEMORY MAPPED)CONTROLSTATUSBUFFERSI/O PROCESSORHOST PORT18SERIAL PORTS(3)DMACONTROLLER 6SPI PORTS(2)UART PORT(1)242Figure 1-1. ADSP-219x/ADSP-2191 DSP Block DiagramFurther, the ADSP-219x addresses the five central requirements for DSPs:• Fast, flexible arithmetic computation units• Unconstrained data flow to and from the computation units• Extended precision and dynamic range in the computation units• Dual address generators with circular buffering support• Efficient program sequencing1-4 ADSP-219x/2191 DSP Hardware Reference

IntroductionUnconstrained Data Flow. The ADSP-219x has a modified Harvardarchitecture combined with a data register file. In every cycle, the DSPcan:• Read two values from memory or write one value to memory• Complete one computation• Write up to three values back to the register fileFast, Flexible Arithmetic. The ADSP-219x family DSPs execute all computationalinstructions in a single cycle. They provide both fast cycletimes and a complete set of arithmetic operations.40-Bit Extended Precision. The DSP handles 16-bit integer and fractionalformats (two’s-complement and unsigned). The processors carry extendedprecision through result registers in their computation units, limitingintermediate data truncation errors.Dual Address Generators. The DSP has two data address generators(DAGs) that provide immediate or indirect (pre- and post-modify)addressing. Modulus and bit-reverse operations are supported with memorypage constraints on data buffer placement only.Efficient Program Sequencing. In addition to zero-overhead loops, theDSP supports quick setup and exit for loops. Loops are both nestable(eight levels in hardware) and interruptable. The processors support bothdelayed and non-delayed branches.ADSP-219x Architecture OverviewAn ADSP-219x is a single-chip microcomputer optimized for digital signalprocessing (DSP) and other high speed numeric processingapplications. These DSPs provide a complete system-on-a-chip, integratinga large, high-speed SRAM and I/O peripherals supported by adedicated DMA bus. The following sections summarize the features ofADSP-219x/2191 DSP Hardware Reference 1-5

ADSP-219x Architecture Overvieweach functional block in the ADSP-219x architecture, which appears inFigure 1-1.The ADSP-2191 combines the ADSP-219x family base architecture (threecomputational units, two data address generators, and a programsequencer) with three serial ports, two SPI-compatible ports, one UARTport, a DMA controller, three programmable timers, general-purpose ProgrammableFlag pins, extensive interrupt capabilities, and on-chipprogram and data memory blocks.The ADSP-2191 architecture is code compatible with ADSP-218x familyDSPs. Though the architectures are compatible, the ADSP-2191 architecturehas a number of enhancements over the ADSP-218x architecture.The enhancements to computational units, data address generators, andprogram sequencer make the ADSP-2191 more flexible and even easier toprogram than the ADSP-218x DSPs.Indirect addressing options provide addressing flexibility—pre-modifywith no update, pre- and post-modify by an immediate 8-bit, two’s-complementvalue and base address registers for easier implementation ofcircular buffering.The ADSP-2191 integrates 64K words of on-chip memory configured as32K words (24-bit) of program RAM, and 32K words (16-bit) of dataRAM. Power-down circuitry is also provided to meet the low power needsof battery operated portable equipment.The ADSP-2191’s flexible architecture and comprehensive instruction setsupport multiple operations in parallel. For example, in one processorcycle, the ADSP-2191 can:• Generate an address for the next instruction fetch• Fetch the next instruction• Perform one or two data moves1-6 ADSP-219x/2191 DSP Hardware Reference

Introduction• Update one or two data address pointers• Perform a computational operationThese operations take place while the processor continues to:• Receive and transmit data through two serial ports• Receive and/or transmit data from a host• Receive or transmit data through the UART• Receive or transmit data over two SPI ports• Access external memory through the external memory interface• Decrement the timersDSP Core ArchitectureThe ADSP-219x instruction set provides flexible data moves and multifunction(one or two data moves with a computation) instructions. Everysingle-word instruction can be executed in a single processor cycle. TheADSP-219x assembly language uses an algebraic syntax for ease of codingand readability. A comprehensive set of development tools supports programdevelopment.Figure 1-1 on page 1-4 shows the architecture of the ADSP-219x core. Itcontains three independent computational units: the ALU, the multiplier/accumulator,and the shifter. The computational units process 16-bitdata from the register file and have provisions to support multiprecisioncomputations. The ALU performs a standard set of arithmetic and logicoperations; division primitives also are supported. The multiplier performssingle-cycle multiply, multiply/add, and multiply/subtractoperations. The multiplier has two 40-bit accumulators, which help withoverflow. The shifter performs logical and arithmetic shifts, normalization,denormalization, and derive exponent operations. The shifter canADSP-219x/2191 DSP Hardware Reference 1-7

ADSP-219x Architecture Overviewefficiently implement numeric format control, including multiword andblock floating-point representations.Register-usage rules influence placement of input and results within thecomputational units. For most operations, the computational units’ dataregisters act as a data register file, permitting any input or result register toprovide input to any unit for a computation. For feedback operations, thecomputational units let the output (result) of any unit be input to anyunit on the next cycle. For conditional or multifunction instructions,there are restrictions limiting which data registers may provide inputs orreceive results from each computational unit. For more information, see“Multifunction Computations” on page 2-58.A powerful program sequencer controls the flow of instruction execution.The sequencer supports conditional jumps, subroutine calls, and lowinterrupt overhead. With internal loop counters and loop stacks, theADSP-2191 executes looped code with zero overhead; no explicit jumpinstructions are required to maintain loops.Two data address generators (DAGs) provide addresses for simultaneousdual operand fetches (from data memory and program memory). EachDAG maintains and updates four 16-bit address pointers. Whenever thepointer is used to access data (indirect addressing), it is pre- or post-modifiedby the value of one of four possible modify registers. A length valueand base address may be associated with each pointer to implement automaticmodulo addressing for circular buffers. Page registers in the DAGsallow circular addressing within 64K word boundaries of each of the 256memory pages, but these buffers may not cross page boundaries. Secondaryregisters duplicate all the primary registers in the DAGs; switchingbetween primary and secondary registers provides a fast context switch.Efficient data transfer in the core is achieved by using internal buses:• Program Memory Address (PMA) Bus• Program Memory Data (PMD) Bus1-8 ADSP-219x/2191 DSP Hardware Reference

Introduction• Data Memory Address (DMA) Bus• Data Memory Data (DMD) Bus• DMA Address Bus• DMA Data BusThe internal address buses share a single external address bus, allowingmemory to be expanded off-chip, and the data buses share a single externaldata bus. Boot memory space and external I/O memory space also sharethe external buses.Program memory can store both instructions and data, permitting theADSP-219x to fetch two operands in a single cycle, one from programmemory and one from data memory. The DSP’s dual memory buses alsolet the ADSP-219x core fetch an operand from data memory and the nextinstruction from program memory in a single cycle.DSP Peripherals ArchitectureFigure 1-1 on page 1-4 shows the DSP’s on-chip peripherals, whichinclude the external memory interface, host port, serial ports, SPI compatibleports, UART port, JTAG test and emulation port, timers, flags, andinterrupt controller. Figure 1-2 illustrates a typical ADSP-2191 systemwith peripheral connections.The ADSP-2191 has a 16-bit host port with DMA capability that providesexternal hosts access to on-chip memory. This parallel port consistsof a multiplexed data/address bus and provides a low-service overhead datamove capability. Configurable for 8- or 16-bit data bus widths, this portprovides a glueless interface to a wide variety of 8- and 16-bit microcontrollers.Two chip-selects provide hosts access to the DSP’s entire memorymap. The DSP is bootable through this port.The ADSP-2191 also has an external memory interface that is shared bythe DSP’s core, the DMA controller, and DMA capable peripherals,ADSP-219x/2191 DSP Hardware Reference 1-9

ADSP-219x Architecture OverviewCLOCKORCRYSTALTIMEROUT ORCAPTUREADSP-2191MCLKIN CLKOUTXTAL ADDR21–0DATA15–8TMR2–0 DATA7–0MS3–0EXTERNALMEMORY(OPTIONAL)ADDR21–0DATA15–8DATA7–0CSCLOCKMULTIPLYANDRANGEBOOTAND OPMODEMSEL6–0/PF6–0DF/PF7BYPASSBMODE1–0OPMODERDWRACKC O N T R O LAD D RE S SD A T AOEWEACKBOOTMEMORY(OPTIONAL)SPORT0ADDR21–0TCLK0DATA15–8TFS0DATA7–0SERIALDEVICE(OPTIONAL)SERIALDEVICE(OPTIONAL)DT0RCLK0RFS0DR0SPORT1TCLK1TFS1DT1RCLK1RFS1BMSBRBGBGHCSOEWEACKEXTERNALI/O MEMORY(OPTIONAL)ADDR21–0DATA15–8DATA7–0DR1IOMSCSSERIALDEVICE(OPTIONAL)SPORT2TCLK2/SCK0TFS2/MOSI0 SPI0DT2/MISO0RCLK2/SCK1RFS2/MOSI1 SPI1OEWEACKHOSTPROCESSOR(OPTIONAL)DR2/MISO1HAD15–0HA16ADDR15–0/DATA15–0ADDR16UARTDEVICE(OPTIONAL)6UARTRXDTXDRESETJTAGHCMSHCIOMSHRDHWRHACKHALEHACK_PCS0CS1RDWRACKALEFigure 1-2. ADSP-219x/ADSP-2191 DSP Block Diagramwhich include the UART port, serial ports, SPI ports, and the host port.The external port consists of an 8- or 16-bit data bus, a 22-bit address bus,and control signals. The data bus is configurable to provide an 8- or 16-bit1-10 ADSP-219x/2191 DSP Hardware Reference

Introductioninterface to external memory. Support for word packing lets the DSPaccess 16- or 24-bit words from external memory regardless of the externaldata bus width. When configured for an 8-bit interface, the unused eightlines provide eight programmable, bidirectional general purpose ProgrammableFlag lines, six of which can be mapped to software conditionsignals.The memory DMA controller lets the ADSP-2191 transfer data to andfrom internal and external memory. On-chip peripherals also can use thisport for DMA transfers to and from memory.The ADSP-2191 can respond to up to 16 interrupt sources at any giventime: three internal (stack, emulator kernel, and power-down), two external(emulator and reset), and twelve user-defined (peripherals) interruptrequests. Programmers assign a peripheral to one of the 12 user definedinterrupt requests. These assignments determine the priority of eachperipheral for interrupt service. Several peripherals can be combined on asingle interrupt request line.There are three serial ports on the ADSP-2191 that provide a completesynchronous, full-duplex serial interface. This interface includes optionalcompanding in hardware and a wide variety of framed or frameless datatransmit and receive modes of operation. Each serial port can transmit orreceive an internal or external, programmable serial clock and frame syncs.Each serial port supports 128-channel Time Division Multiplexing.The ADSP-2191 provides up to sixteen general-purpose I/O pins, whichare programmable as either inputs or outputs. Eight of these pins are dedicatedgeneral purpose Programmable Flag pins. The other eight aremultifunctional pins, acting as general purpose I/O pins when the DSPconnects to an 8-bit external data bus and acting as the upper eight datapins when the DSP connects to a 16-bit external data bus. These ProgrammableFlag pins can implement edge- or level-sensitive interrupts. Theexecution of conditional instructions can be based on some of the ProgrammableFlag pins.ADSP-219x/2191 DSP Hardware Reference 1-11

ADSP-219x Architecture OverviewThree programmable interval timers generate periodic interrupts. Eachtimer can be independently set to operate in one of three modes:• Pulse Waveform Generation mode• Pulse Width Count/Capture mode• External Event Watchdog modeEach timer has one bi-directional pin and four registers that implement itsmode of operation: a configuration register, a count register, a period register,and a pulsewidth register. A single status register supports all threetimers. A bit in the mode status register globally enables or disables allthree timers, and a bit in each timer’s configuration register enables or disablesthe corresponding timer independently of the others.Memory ArchitectureThe ADSP-2191 provides 64K words of on-chip memory. This memory isdivided into two 32K blocks located on memory Page 0 in the DSP’smemory map. In addition to the internal and external memory space, theADSP-2191 can address two additional and separate memory spaces: I/Ospace and boot space.As shown in Figure 1-3, the DSP’s two internal memory blocks populateall of Page 0. The entire DSP memory map consists of 256 pages (pages0−255), and each page is 64K words long. External memory space consistsof four memory banks (banks 3–0) and supports a wide variety of SRAMmemory devices. Each bank is selectable using the memory select pins(MS3-0) and has configurable page boundaries, waitstates, and waitstatemodes. The 1K word of on-chip boot-ROM populates the lower 1Kaddresses of page 255. Other than page 0 and page 255, the remaining254 pages are addressable off-chip. I/O memory pages differ from externalmemory pages in that I/O pages are 1K word long, and the external I/Opages have their own select pin (IOMS). Pages 0–7 of I/O memory spacereside on-chip and contain the configuration registers for the peripherals.1-12 ADSP-219x/2191 DSP Hardware Reference

IntroductionBoth the DSP core and DMA-capable peripherals can access the DSP’sentire memory map.INTERNALMEMORY64K WORDMEMORYPAGESPAGE 255RESERVEDBOOT ROM, 24-BITADDRESS0xFF FFFF0xFF 04000xFF 0000LOWER PAGE BOUNDARIESARE CONFIGURABLE FORBANKS OF EXTERNALMEMORY.BOUNDARIES SHOWN AREBANK SIZES AT RESET.ADDRESS0xFE FFFFMEMORY SELECTS (MS)FOR PORTIONS OFTHE MEMORY MAPAPPEARWITH THE SELECTEDMEMORY.EXTERNALMEMORY(16- BIT)PAGES 192–254PAGES 128–191PAGES 64–127BANK3(MS3)BANK2(MS2)BANK1(MS1)0xC0 00000x80 0000BOOTMEMORY16- BIT(BMS)I/O MEMORY16- BIT1K WORDPAGES 8–255INTERNALMEMORYPAGES 1–63PAGE 0BANK0(MS0)BLOCK1, 16-BITBLOCK0, 24-BIT0x40 00000x01 00000x00 80000x00 000064K WORDPAGES 1–2540x01 00001K WORDPAGES 0–7EXTERNAL(IOMS)INTERNALADDRESS0xFF : 0x3FF0x08 : 0x0000x00 : 0x000Figure 1-3. ADSP-2191 Internal/External Memory, Boot Memory, andI/O Memory MapsInternal (On-chip) MemoryThe ADSP-2191’s unified program and data memory space consists of16M locations that are accessible through two 24-bit address buses, thePMA and DMA buses. The DSP uses slightly different mechanisms toADSP-219x/2191 DSP Hardware Reference 1-13

ADSP-219x Architecture Overviewgenerate a 24-bit address for each bus. The DSP has three functions thatsupport access to the full memory map.• The DAGs generate 24-bit addresses for data fetches from the entireDSP memory address range. Because DAG index (address) registersare 16 bits wide and hold the lower 16-bits of the address, each ofthe DAGs has its own 8-bit page register (DMPGx) to hold the mostsignificant eight address bits. Before a DAG generates an address,the program must set the DAG’s DMPGx register to the appropriatememory page.• The program sequencer generates the addresses for instructionfetches. For relative addressing instructions, the program sequencerbases addresses for relative jumps, calls, and loops on the 24-bit ProgramCounter (PC). For direct addressing instructions (two-wordinstructions), the instruction provides an immediate 24-bit addressvalue. The PC allows linear addressing of the full 24 bit addressrange.• The program sequencer relies on an 8-bit Indirect Jump page (IJPG)register to supply the most significant eight address bits for indirectjumps and calls that use a 16-bit DAG address register for part ofthe branch address. Before a cross page jump or call, the programmust set the program sequencer’s IJPG register to the appropriatememory page.The ADSP-2191 has 1K word of on-chip ROM that holds boot routines.If peripheral booting is selected, the DSP starts executing instructionsfrom the on-chip boot ROM, which starts the boot process from theselected peripheral. For more information, see “Booting Modes” on page1-21. The on-chip boot ROM is located on Page 255 in the DSP’s memorymap.The ADSP-2191 has internal I/O memory for peripheral control and statusregisters. For more information, see the I/O memory space discussionon page 1-15.1-14 ADSP-219x/2191 DSP Hardware Reference

IntroductionExternal (Off-chip) MemoryEach of the ADSP-2191’s off-chip memory spaces has a separate controlregister, so applications can configure unique access parameters for eachspace. The access parameters include read and write wait counts, waitstatecompletion mode, I/O clock divide ratio, write hold time extension,strobe polarity, and data bus width. The core clock and peripheral clockratios influence the external memory access strobe widths. For more information,see “Clock Signals” on page 1-20. The off-chip memory spacesare:• External memory space (MS3-0 pins)• I/O memory space (IOMS pin)• Boot memory space (BMS pin)All of these off-chip memory spaces are accessible through the externalport, which can be configured for 8-bit or 16-bit data widths.External Memory Space. External memory space consists of four memorybanks. These banks can contain a configurable number of 64K wordpages. At reset, the page boundaries for external memory have Bank 0 containingpages 1−63, Bank 1 containing pages 64−127, Bank 2 containingpages 128−191, and Bank 3 containing pages 192−254. The MS3-0 memorybank pins select Bank 3-0, respectively. The external memory interfacedecodes the eight MSBs of the DSP program address to select one of thefour banks. Both the DSP core and DMA-capable peripherals can accessthe DSP’s external memory space.I/O Memory Space. The ADSP-2191 supports an additional externalmemory called I/O memory space. This space is designed to support simpleconnections to peripherals (such as data converters and externalregisters) or to bus interface ASIC data registers. I/O space supports a totalof 256K locations. The first 8K addresses are reserved for on-chip peripherals.The upper 248K addresses are available for external peripheraldevices and are selected with the IOMS pin. The DSP’s instruction set pro-ADSP-219x/2191 DSP Hardware Reference 1-15

ADSP-219x Architecture Overviewvides instructions for accessing I/O space. These instructions use an 18-bitaddress that is assembled from an 8-bit I/O page (IOPG) register and a10-bit immediate value supplied in the instruction. Both the ADSP-219xcore and a host (through the host port) can access I/O memory space.Boot Memory Space. Boot memory space consists of one off-chip bankwith 253 pages. The BMS pin selects boot memory space. Both the DSPcore and DMA-capable peripherals can access the DSP’s off-chip bootmemory space. If the DSP is configured to boot from boot memory space,the DSP starts executing instructions from the on-chip boot ROM, whichstarts booting the DSP from boot memory. For more information, see“Booting Modes” on page 1-21.InterruptsThe interrupt controller lets the DSP respond to seventeen interrupts withminimum overhead. The controller implements an interrupt priorityscheme that lets programs assign interrupt priorities to each peripheral.For more information, see “ADSP-2191 Interrupts” on page C-1.DMA ControllerThe ADSP-2191 has a DMA controller that supports automated datatransfers with minimal overhead for the DSP core. Cycle stealing DMAtransfers can occur between the ADSP-2191’s internal memory and any ofits DMA capable peripherals. Additionally, DMA transfers also can beaccomplished between any of the DMA capable peripherals and externaldevices connected to the external memory interface. DMA capable peripheralsinclude the host port, serial ports, SPI ports, UART port, andmemory-to-memory (memDMA) DMA channel. Each individual DMAcapable peripheral has one or more dedicated DMA channels. For adescription of each DMA sequence, the DMA controller uses a set ofparameters—called a DMA descriptor. When successive DMA sequencesare needed, these descriptors can be linked or chained together. When1-16 ADSP-219x/2191 DSP Hardware Reference

Introductionchained, the completion of one DMA sequence auto-initiates and startsthe next sequence. DMA sequences do not contend for bus access with theDSP core, instead DMAs “steal” cycles to access memory.Host PortThe ADSP-2191’s host port functions as a slave on the external bus of anexternal host. The host port interface lets a host read from or write to theDSP’s memory space, boot space, or internal I/O space. Examples of hostsinclude external microcontrollers, microprocessors, or ASICs.The host port is a multiplexed address and data bus that provides an 8- or16-bit data path and operates using an asynchronous transmission protocol.To access the DSP’s internal memory space, a host steals one cycle peraccess from the DSP. A host access to the DSP’s external memory uses theexternal port interface and does not stall (or steal cycles from) the DSP’score. Because a host can access internal I/O memory space, a host can controlany of the DSP’s I/O mapped peripherals.DSP Serial Ports (SPORTs)The ADSP-2191 incorporates three complete synchronous serial ports(SPORT0, SPORT1, and SPORT2) for serial and multiprocessor communications.The SPORTs support the following features:• Bidirectional operation—each SPORT has independent transmitand receive pins.• Buffered (eight-deep) transmit and receive ports—each port has adata register for transferring data words to and from other DSPcomponents and shift registers for shifting data in and out of thedata registers.• Clocking—each transmit and receive port either can use an externalserial clock (≤75 MHz) or generate its own, in frequencies rangingfrom 1144 Hz to 75 MHz.ADSP-219x/2191 DSP Hardware Reference 1-17

ADSP-219x Architecture Overview• Word length—each SPORT supports serial data words from 3- to16-bits in length transferred in big endian (MSB) or little endian(LSB) format.• Framing—each transmit and receive port can run with or withoutframe sync signals for each data word.• Companding in hardware—each SPORT can perform A-law orµ-law companding, according to ITU recommendation G.711.• DMA operations with single-cycle overhead—each SPORT canautomatically receive and transmit multiple buffers of memory data,one data word each DSP cycle.• Interrupts—each transmit and receive port generates an interruptupon completing the transfer of a data word or after transferring anentire data buffer or buffers through DMA.• Multichannel capability—each SPORT supports the H.100 standard.Serial Peripheral Interface (SPI) PortsThe DSP has two SPI-compatible ports, which enable the DSP to communicatewith multiple SPI compatible devices. These ports aremultiplexed with SPORT2, so either SPORT2 or the SPI ports are activedepending on the state of the OPMODE pin or OPMODE bit. To change themode, the pin can be changed during hardware or software reset, or the bitcan be changed at runtime.The SPI interface uses three pins for transferring data: two data pins (MasterOutput-Slave Input, MOSIx, and Master Input-Slave Output, MISOx)and a clock pin (Serial Clock, SCKx). Two SPI chip select input pins(SPISSx) let other SPI devices select the DSP, and fourteen SPI chip selectoutput pins (SPIxSEL7-1) let the DSP select other SPI devices. The SPIselect pins are re-configured Programmable Flag pins. Using these pins,1-18 ADSP-219x/2191 DSP Hardware Reference

Introductionthe SPI ports provide a full duplex, synchronous serial interface, whichsupports both master and slave modes and multiple master environments.Each SPI port’s baud rate and clock phase/polarities are programmable,and each has an integrated DMA controller, configurable to support bothtransmit and receive data streams. The SPI’s DMA controller can only serviceuni-directional accesses at any given time.During transfers, the SPI ports simultaneously transmit and receive byserially shifting data in and out on their two serial data lines. The serialclock line synchronizes the shifting and sampling of data on the two serialdata lines.UART PortThe UART port provides a simplified UART interface to another peripheralor host. It performs full duplex, asynchronous transfers of serial data.The UART port supports two modes of operation:• PIO (programmed I/O)• DMA (direct memory access)Programmable Flag (PFx) PinsThe ADSP-2191 has sixteen bi-directional, general-purpose I/O, ProgrammableFlag (PF15-0) pins. The PF7-0 pins are dedicated togeneral-purpose I/O. The PF15-8 pins serve either as general-purpose I/Opins (if the DSP is connected to an 8-bit external data bus) or serve asDATA15-8 lines (if the DSP is connected to a 16-bit external data bus). TheProgrammable Flag pins have special functions for clock multiplier selectionand for SPI port operation.ADSP-219x/2191 DSP Hardware Reference 1-19

ADSP-219x Architecture OverviewLow-Power OperationThe ADSP-2191 has four low-power options that significantly reduce thepower dissipation when the device operates under standby conditions. Toenter any of these modes, the DSP executes an IDLE instruction. TheADSP-2191 uses configuration of the bits in the PLLCTL register to selectbetween the low-power modes as the DSP executes the Idle. Dependingon the mode, an Idle shuts off clocks to different parts of the DSP in thedifferent modes. The low-power modes are:• Idle• Powerdown Core• Powerdown Core/Peripherals• Powerdown AllClock SignalsThe ADSP-2191 can be clocked by a crystal oscillator or a buffered,shaped clock derived from an external clock oscillator. If a crystal oscillatoris used, the crystal should be connected across the CLKIN and XTAL pins,with two capacitors connected. Capacitor values are dependent on crystaltype and should be specified by the crystal manufacturer. A parallel-resonant,fundamental frequency, microprocessor-grade crystal should be usedfor this configuration.If a buffered, shaped clock is used, this external clock connects to theDSP’s CLKIN pin. CLKIN input cannot be halted, changed, or operatedbelow the specified frequency during normal operation. This clock signalshould be a TTL-compatible signal. When an external clock is used, theXTAL input must be left unconnected.1-20 ADSP-219x/2191 DSP Hardware Reference

IntroductionThe DSP provides a user programmable 1x to 31x multiplication of theinput clock—including some fractional values—to support 128 external-to-internal(DSP core) clock ratios.Booting ModesThe ADSP-2191 has seven mechanisms for automatically loading internalprogram memory after reset. The BMODE2-0 pins, sampled during hardwarereset, and three bits in the Reset Configuration Register implement thesemodes:JTAG Port• Boot from 16-bit external memory• Boot from 8-bit EPROM• Boot from host• Execute from 8-bit external memory (No Boot)• Boot from UART• Boot from SPI 4 kbits• Boot from SPI 512 kbitsThe JTAG port on the ADSP-2191 supports the IEEE standard 1149.1Joint Test Action Group (JTAG) standard for system test. This standarddefines a method for serially scanning the I/O status of each component ina system. Emulators use the JTAG port to monitor and control the DSPduring emulation. Emulators using this port provide full-speed emulationwith access to inspect and modify memory, registers, and processor stacks.JTAG-based emulation is non-intrusive and does not affect target systemloading or timing.ADSP-219x/2191 DSP Hardware Reference 1-21

Development ToolsDevelopment ToolsThe ADSP-219x is supported by VisualDSP®, an easy-to-use projectmanagement environment, comprised of an Integrated DevelopmentEnvironment (IDE) and Debugger. VisualDSP lets you manage projectsfrom start to finish from within a single, integrated interface. Because theproject development and debug environments are integrated, you canmove easily between editing, building, and debugging activities.Flexible Project Management. The IDE provides flexible project managementfor the development of DSP applications. The IDE includes accessto all the activities necessary to create and debug DSP projects. You cancreate or modify source files or view listing or map files with the IDE Editor.This powerful Editor is part of the IDE and includes multiplelanguage syntax highlighting, OLE drag and drop, bookmarks, and standardediting operations such as undo/redo, find/replace, copy/paste/cut,and go to.Also, the IDE includes access to the DSP C Compiler, C RuntimeLibrary, Assembler, Linker, Loader, Simulator, and Splitter. You specifyoptions for these Tools through Property Page dialogs. Property Page dialogsare easy to use and make configuring, changing, and managing yourprojects simple. These options control how the tools process inputs andgenerate outputs, and the options have a one-to-one correspondence tothe tools’ command line switches. You can define these options once ormodify them to meet changing development needs. You also can accessthe Tools from the operating system command line if you choose.Greatly Reduced Debugging Time. The Debugger has an easy-to-use,common interface for all processor simulators and emulators availablethrough Analog Devices and third parties or custom developments. TheDebugger has many features that greatly reduce debugging time. You canview C source interspersed with the resulting Assembly code. You can profileexecution of a range of instructions in a program; set simulatedwatchpoints on hardware and software registers, program and data mem-1-22 ADSP-219x/2191 DSP Hardware Reference

Introductionory; and trace instruction execution and memory accesses. These featuresenable you to correct coding errors, identify bottlenecks, and examineDSP performance. You can use the custom register option to select anycombination of registers to view in a single window. The Debugger canalso generate inputs, outputs, and interrupts so you can simulate realworld application conditions.Software Development Tools. Software Development Tools, which supportthe ADSP-219x family, let you develop applications that take fulladvantage of the architecture, including shared memory and memoryoverlays. Software Development Tools include C Compiler, C RuntimeLibrary, DSP and Math Libraries, Assembler, Linker, Loader, Simulator,and Splitter.C/C++ Compiler & Assembler. The C/C++ Compiler generates efficientcode that is optimized for both code density and execution time. TheC/C++ Compiler allows you to include Assembly language statementsinline. Because of this, you can program in C and still use Assembly fortime-critical loops. You can also use pretested Math, DSP, and C RuntimeLibrary routines to help shorten your time to market. The ADSP-219xfamily assembly language is based on an algebraic syntax that is easy tolearn, program, and debug.Linker & Loader. The Linker provides flexible system definition throughLinker Description Files (.LDF). In a single LDF, you can define differenttypes of executables for a single or multiprocessor system. The Linkerresolves symbols over multiple executables, maximizes memory use, andeasily shares common code among multiple processors. The Loader supportscreation of PROM, host, SPI, and UART boot images. The Loaderallows multiprocessor system configuration with smaller code and fasterboot time.3rd-Party Extensible. The VisualDSP environment enables third-partycompanies to add value using Analog Devices’ published set of ApplicationProgramming Interfaces (API). Third party products—realtimeoperating systems, emulators, high-level language compilers, multiproces-ADSP-219x/2191 DSP Hardware Reference 1-23

Differences from Previous DSPssor hardware —can interface seamlessly with VisualDSP therebysimplifying the tools integration task. VisualDSP follows the COM APIformat. Two API tools, Target Wizard and API Tester, are also availablefor use with the API set. These tools help speed the time-to-market forvendor products. Target Wizard builds the programming shell based onAPI features the vendor requires. The API tester exercises the individualfeatures independently of VisualDSP. Third parties can use a subset ofthese APIs that meet their application needs. The interfaces are fully supportedand backward compatible.Further details and ordering information are available in the VisualDSPDevelopment Tools data sheet. This data sheet can be requested from anyAnalog Devices sales office or distributor.Differences from Previous DSPsThis section identifies differences between the ADSP-219x DSPs and previousADSP-2100 family DSPs: ADSP-210x, ADSP-211x, ADSP-217x,and ADSP-218x. The ADSP-219x preserves much of the core ADSP-2100family architecture, while extending performance and functionality. Forbackground information on previous ADSP-2100 family DSPs, see theADSP-2100 Family User’s Manual.The following sections describe key differences and enhancements of theADSP-219x over previous ADSP-2100 family DSPs. These enhancementsalso lead to some differences in the instruction sets between these DSPs.For more information, see the ADSP-219x DSP Instruction Set Reference.Computational Units and Data Register FileThe ADSP-219x DSP’s computational units differ from theADSP-218x’s, because the ADSP-219x data registers act as a register filefor unconditional, single-function instructions. In these instructions, anydata register may be an input to any computational unit. For conditional1-24 ADSP-219x/2191 DSP Hardware Reference

Introductionand/or multifunction instructions, the ADSP-219x and ADSP-218x DSPfamilies have the same data register usage restrictions — AX and AY forALU, MX and MY for the multiplier, and SI for shifter inputs. For moreinformation, see “Computational Units” on page 2-1.Arithmetic Status (ASTAT) Register LatencyThe ADSP-219x ASTAT register has a one cycle effect latency. This issue isdiscussed on page 2-18.Norm and Exp Instruction ExecutionThe ADSP-219x Norm and Exp instructions execute slightly differentlyfrom previous ADSP-218x DSPs. This issue is discussed on page 2-45.Shifter Result (SR) Register as Multiplier Dual AccumulatorThe ADSP-219x architecture introduces a new 16-bit register in additionto the SR0 and SR1 registers, the combination of which comprise the 40-bitwide SR register on the ADSP-218x DSPs. This new register, called SR2,can be used in multiplier or shift operations (lower 8 bits) and as a full16-bit-wide scratch register. As a result, the ADSP-219x DSP has two40-bit-wide accumulators, MR and SR. The SR dual accumulator hasreplaced the multiplier feedback register MF, as shown in the followingexample:ADSP-218x InstructionMF=MR+MX0*MY1(UU);IF NOT MV MR=AR*MF;ADSP-219x Instruction (Replacement)SR=MR+MX0*MY1(UU);IF NOT MV MR=AR*SR2;Shifter Exponent (SE) Register is not Memory AccessibleThe ADSP-218x DSPs use SE as a data or scratch register. The SE registerof the ADSP-219x architecture is not accessible from the data or programADSP-219x/2191 DSP Hardware Reference 1-25

Differences from Previous DSPsmemory buses. Therefore, the multifunction instructions of theADSP-218x that use SE as a data or scratch register, should use one of thedata file registers (DREG) as a scratch register on the ADSP-219x DSP.ADSP-218x InstructionSR=Lshift MR1(HI),SE=DM(I6,M5);ADSP-219x Instruction (Replacement)SR=Lshift MR1(HI),AX0=DM(I6,M5);Conditions (SWCOND) and Condition Code (CCODE) RegisterThe ADSP-219x DSP changes support for the ALU Signed (AS) conditionand supports additional arithmetic and status condition testing with theCondition Code (CCODE) register and Software Condition (SWCOND) test.The two conditions are SWCOND and Not SWCOND. The usage of theADSP-219x’s and most ADSP-218x’s arithmetic conditions (EQ, NE, GE,GT, LE, LT, AV, Not AV, AC, Not AC, MV, Not MV) are compatible.The new Shifter Overflow (SV) condition of the ADSP-219x architectureis a good example of how the CCODE register and SWCOND test work. TheADSP-219x DSP’s Arithmetic Status (ASTAT) register contains a bit indicatingthe status of the shifter’s result. The shifter is a computational unitthat performs arithmetic or logical bitwise shifts on fields within a dataregister. The result of the operation goes into the Shifter Result (SR2, SR1,and SR0, which are combined into SR) register. If the result overflows theSR register, the Shifter Overflow (SV) bit in the ASTAT register records thisoverflow/underflow condition for the SR result register (0 = No overflowor underflow, 1 = Overflow or underflow).For the most part, bits (status condition indicators) in the ASTAT registercorrespond to condition codes that appear in conditional instructions. Forexample, the AZ (ALU Zero) bit in ASTAT corresponds to the EQ (ALUresult equals zero) condition and would be used in code like this:IF EQ AR = AX0 + AY0;/* if the ALU result (AR) register is zero, add AX0 and AY0 */1-26 ADSP-219x/2191 DSP Hardware Reference

IntroductionThe SV status condition in the ASTAT bits does not correspond to a conditioncode that can be directly used in a conditional instruction. To test forthis status condition, software selects a condition to test by loading a valueinto the Condition Code (CCODE) register and uses the Software Condition(SWCOND) condition code in the conditional instruction. The DSP codewould look like this:CCODE = 0x09; Nop;// set CCODE for SV conditionIF SWCOND SR = MR0 * SR1 (UU); // mult unsigned X and YThe Nop after loading the CCODE register accommodates the one cycle effectlatency of the CCODE register.The ADSP-218x DSP supports two conditions to detect the sign of theALU result. On the ADSP-219x, these two conditions (Pos and Neg) aresupported as AS and Not AS conditions in the CCODE register. For moreinformation on CCODE register values and SWCOND conditions, see “ConditionalSequencing” on page 3-39.Unified Memory SpaceThe ADSP-219x architecture has a unified memory space with separatememory blocks to differentiate between 24- and 16-bit memory. In theunified memory, the term program or data memory only has semantic significance;the address determines the “PM” or “DM” functionality. It is bestto revise any code with non-symbolic addressing in order to use the newtools.Data Memory Page (DMPG1 and DMPG2) RegistersThe ADSP-219x processor introduces a paged memory architecture thatuses 16-bit DAG registers to access 64K pages. The 16-bit DAG registerscorrespond to the lower 16 bits of the DSP’s address buses, which are24-bit wide. To store the upper 8 bits of the 24-bit address, theADSP-219x DSP architecture uses two additional registers, DMPG1 andADSP-219x/2191 DSP Hardware Reference 1-27

Differences from Previous DSPsDMPG2. DMPG1 and DMPG2 work with the DAG registers I0-I3 and I4-I7,respectively.Data Address Generator (DAG) Addressing ModesThe ADSP-219x architecture provides additional flexibility over theADSP-218x DSP family in DAG addressing modes:• Pre-modify without update addressing in addition to the post-modifywith update mode of the ADSP-218x instruction set:DM(IO+M1) = AR; /* pre-modify syntax */DM(IO+=M1) = AR; /* post-modify syntax */• Pre-modify and post-modify with an 8-bit two’s-complementimmediate modify value instead of an M register:AX0 = PM(I5+-4); /* pre-modify syntax (for modifier = -4)*/AX0 = PM(I5+=4); /* post-modify syntax (for modifier = 4) */• DAG modify with an 8-bit two’s-complement immediate-modifyvalue:Modify(I7+=0x24);Base Registers for Circular BuffersThe ADSP-219x processor eliminates the existing hardware restriction ofthe ADSP-218x DSP architecture on a circular buffer starting address.ADSP-219x enables declaration of any number of circular buffers by designatingB0-B7 as the base registers for addressing circular buffers; thesebase registers are mapped to the “register” space on the core.1-28 ADSP-219x/2191 DSP Hardware Reference

IntroductionProgram Sequencer, Instruction Pipeline, and StacksThe ADSP-219x DSP core and inputs to the sequencer differ for variousmembers of the ADSP-219x family DSPs. The main differences betweenthe ADSP-218x and ADSP-219x sequencers are that the ADSP-219xsequencer has:• A 6-stage instruction pipeline, which works with the sequencer’sloop and PC stacks, conditional branching, interrupt processing,and instruction caching.• A wider branch execution range, supporting:• 13-bit, non-delayed or delayed relative conditional Jump• 16-bit, non-delayed or delayed relative unconditional Jumpor Call• Conditional non-delayed or delayed indirect Jump or Callwith address pointed to by a DAG register• 24-bit conditional non-delayed absolute long Jump or Call• A narrowing of the Do/Until termination conditions to CounterExpired (CE) and Forever.Conditional Execution (Difference in Flag Input Support)Unlike the ADSP-218x DSP family, ADSP-219x processors do notdirectly support a conditional Jump/Call based on flag input. Instead, theADSP-219x supports this type of conditional execution with the CCODEregister and SWCOND condition. For more information, see “Conditions(SWCOND) and Condition Code (CCODE) Register” on page 1-26.ADSP-219x/2191 DSP Hardware Reference 1-29

Differences from Previous DSPsThe ADSP-219x architecture has 16 programmable flag pins that can beconfigured as either inputs or outputs. The flags can be checked either byreading the FLAGS register, or by using a software condition flag.ADSP-218x InstructionIf Not FLAG_IN AR=MR0 And 8192;ADSP-219x Instruction (Replacement)SWCOND=0x03;If Not SWCOND AR=MR0 And 8192;IOPG = 0x06;AX0=IO(FLAGS);AXO=Tstbit 11 OF AXO;If EQ AR=MRO And 8192;Execution Latencies (Different for JUMP Instructions)The ADSP-219x processor has an instruction pipeline (unlike ADSP-218xDSPs) and branches execution for immediate Jump and Call instructionsin four clock cycles if the branch is taken. To minimize branch latency,ADSP-219x programs can use the delayed branch option on jumps andcalls, reducing branch latency by two cycles. This savings comes from executionof two instructions following the branch before the Jump/Calloccurs.Instruction Set EnhancementsADSP-219x provides near source code compatibility with the previousfamily members, easing the process of porting code. All computationalinstructions (but not all registers) from previous ADSP-2100 family DSPs1-30 ADSP-219x/2191 DSP Hardware Reference

Introductionare available in ADSP-219x. New instructions, control registers, or otherfacilities, required to support the new feature set of ADSP-219x core are:• Program flow control differences (pipeline execution and changes tolooping)• Memory accessing differences (DAG support and memory map)• Peripheral I/O differences (additional ports and added DMA functionality)For more information, see the ADSP-219x DSP Instruction Set Reference.For more Information about AnalogProductsAnalog Devices is online on the internet at http://www.analog.com. OurWeb pages provide information on the company and products, includingaccess to technical information and documentation, product overviews,and product announcements.You may also obtain additional information about Analog Devices and itsproducts in any of the following ways:• Visit our World Wide Web site at www.analog.com• FAX questions or requests for information to 1(781)461-3010.• Access the DSP Division File Transfer Protocol (FTP) site at ftpftp.analog.com or ftp 137.71.23.21 or ftp://ftp.analog.com.ADSP-219x/2191 DSP Hardware Reference 1-31

For Technical or Customer SupportFor Technical or Customer SupportYou can reach our Customer Support group in the following ways:• E-mail questions to dsp.support@analog.com ordsp.europe@analog.com (European customer support)• Telex questions to 924491, TWX:710/394-6577• Cable questions to ANALOG NORWOODMASS• Contact your local ADI sales office or an authorized ADI distributor• Send questions by mail to:Analog Devices, Inc.DSP DivisionOne Technology WayP.O. Box 9106Norwood, MA 02062-9106USAWhat’s New in this ManualThis is the first edition of the ADSP-219x DSP Hardware Reference. Summariesof changes between editions will start with the next edition.Related DocumentsFor more information about Analog Devices DSPs and developmentproducts, see the following documents:• ADSP-2191 DSP Microcomputer Data Sheet• ADSP-219x DSP Instruction Set Reference• VisualDSP++ User’s Guide for ADSP-21xx Family DSPs1-32 ADSP-219x/2191 DSP Hardware Reference

Introduction• C Compiler and Library Manual for ADSP-219x Family DSPs• Assembler and Preprocessor Manual for ADSP-219x Family DSPs• Linker and Utilities Manual for ADSP-219x Family DSPs• Getting Started Guide for ADSP-219x Family DSPsAll the manuals are included in the software distribution CD-ROM. Toaccess these manuals, use the Help Topics command in the VisualDSP++environment’s Help menu and select the Online Manuals. From this Helptopic, you can open any of the manuals, which are in Adobe Acrobat PDFformat.ConventionsThe following are conventions that apply to all chapters. Note that additionalconventions, which apply only to specific chapters, appearthroughout this document.Table 1-1. Notation ConventionsExampleAX0, SR, PXTMR0E, RESETDRx, MS3-0If, Do/UntilDescriptionRegister names appear in UPPERCASE and keyword fontPin names appear in UPPERCASE and keyword font; activelow signals appear with an OVERBAR.Register and pin names in the text may refer to groups of registersor pins. When a lowercase “x” appears in a register name(e.g., DRx), that indicates a set of registers (e.g., DR0, DR1, andDR2). A range also may be shown with a hyphen (e.g., MS3-0indicates MS3, MS2, MS1, and MS0).Assembler instructions (mnemonics) appear in Mixed-case andkeyword fontADSP-219x/2191 DSP Hardware Reference 1-33

ConventionsTable 1-1. Notation ConventionsExample[this,that]|this,that|0xabcd, b#1111i̸DescriptionAssembler instruction syntax summaries show optional itemstwo ways. When the items are optional and none is required,the list is shown enclosed in square brackets, []. When thechoices are optional, but one is required, the list is shownenclosed in vertical bars, ||.A 0x prefix indicates hexadecimal; a b# prefix indicates binaryA note, providing information of special interest or identifyinga related DSP topic.A caution, providing information on critical design or programmingissues that influence operation of the DSP.Click HereIn the online version of this document, a cross reference acts asa hypertext link to the item being referenced. Click on blue references(Table, Figure, or section names) to jump to the location.1-34 ADSP-219x/2191 DSP Hardware Reference