ADSP-219x/2191 DSP Hardware Reference, Introduction

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ADSP-219x Architecture Overviewefficiently implement numeric format control, including multiword andblock floating-point representations.Register-usage rules influence placement of input and results within thecomputational units. For most operations, the computational units’ dataregisters act as a data register file, permitting any input or result register toprovide input to any unit for a computation. For feedback operations, thecomputational units let the output (result) of any unit be input to anyunit on the next cycle. For conditional or multifunction instructions,there are restrictions limiting which data registers may provide inputs orreceive results from each computational unit. For more information, see“Multifunction Computations” on page 2-58.A powerful program sequencer controls the flow of instruction execution.The sequencer supports conditional jumps, subroutine calls, and lowinterrupt overhead. With internal loop counters and loop stacks, theADSP-2191 executes looped code with zero overhead; no explicit jumpinstructions are required to maintain loops.Two data address generators (DAGs) provide addresses for simultaneousdual operand fetches (from data memory and program memory). EachDAG maintains and updates four 16-bit address pointers. Whenever thepointer is used to access data (indirect addressing), it is pre- or post-modifiedby the value of one of four possible modify registers. A length valueand base address may be associated with each pointer to implement automaticmodulo addressing for circular buffers. Page registers in the DAGsallow circular addressing within 64K word boundaries of each of the 256memory pages, but these buffers may not cross page boundaries. Secondaryregisters duplicate all the primary registers in the DAGs; switchingbetween primary and secondary registers provides a fast context switch.Efficient data transfer in the core is achieved by using internal buses:• Program Memory Address (PMA) Bus• Program Memory Data (PMD) Bus1-8 ADSP-219x/2191 DSP Hardware Reference
Introduction• Data Memory Address (DMA) Bus• Data Memory Data (DMD) Bus• DMA Address Bus• DMA Data BusThe internal address buses share a single external address bus, allowingmemory to be expanded off-chip, and the data buses share a single externaldata bus. Boot memory space and external I/O memory space also sharethe external buses.Program memory can store both instructions and data, permitting theADSP-219x to fetch two operands in a single cycle, one from programmemory and one from data memory. The DSP’s dual memory buses alsolet the ADSP-219x core fetch an operand from data memory and the nextinstruction from program memory in a single cycle.DSP Peripherals ArchitectureFigure 1-1 on page 1-4 shows the DSP’s on-chip peripherals, whichinclude the external memory interface, host port, serial ports, SPI compatibleports, UART port, JTAG test and emulation port, timers, flags, andinterrupt controller. Figure 1-2 illustrates a typical ADSP-2191 systemwith peripheral connections.The ADSP-2191 has a 16-bit host port with DMA capability that providesexternal hosts access to on-chip memory. This parallel port consistsof a multiplexed data/address bus and provides a low-service overhead datamove capability. Configurable for 8- or 16-bit data bus widths, this portprovides a glueless interface to a wide variety of 8- and 16-bit microcontrollers.Two chip-selects provide hosts access to the DSP’s entire memorymap. The DSP is bootable through this port.The ADSP-2191 also has an external memory interface that is shared bythe DSP’s core, the DMA controller, and DMA capable peripherals,ADSP-219x/2191 DSP Hardware Reference 1-9
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Page 5 and 6: IntroductionUnconstrained Data Flow
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Page 13 and 14: IntroductionBoth the DSP core and D
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Page 19 and 20: Introductionthe SPI ports provide a
Page 21 and 22: IntroductionThe DSP provides a user
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Page 27 and 28: IntroductionThe SV status condition
Page 29 and 30: IntroductionProgram Sequencer, Inst
Page 31 and 32: Introductionare available in ADSP-2
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