ADSP-219x/2191 DSP Hardware Reference, Introduction

ADSP-219x Architecture Overviewvides instructions for accessing I/O space. These instructions use an 18-bitaddress that is assembled from an 8-bit I/O page (IOPG) register and a10-bit immediate value supplied in the instruction. Both the ADSP-219xcore and a host (through the host port) can access I/O memory space.Boot Memory Space. Boot memory space consists of one off-chip bankwith 253 pages. The BMS pin selects boot memory space. Both the DSPcore and DMA-capable peripherals can access the DSP’s off-chip bootmemory space. If the DSP is configured to boot from boot memory space,the DSP starts executing instructions from the on-chip boot ROM, whichstarts booting the DSP from boot memory. For more information, see“Booting Modes” on page 1-21.InterruptsThe interrupt controller lets the DSP respond to seventeen interrupts withminimum overhead. The controller implements an interrupt priorityscheme that lets programs assign interrupt priorities to each peripheral.For more information, see “ADSP-2191 Interrupts” on page C-1.DMA ControllerThe ADSP-2191 has a DMA controller that supports automated datatransfers with minimal overhead for the DSP core. Cycle stealing DMAtransfers can occur between the ADSP-2191’s internal memory and any ofits DMA capable peripherals. Additionally, DMA transfers also can beaccomplished between any of the DMA capable peripherals and externaldevices connected to the external memory interface. DMA capable peripheralsinclude the host port, serial ports, SPI ports, UART port, andmemory-to-memory (memDMA) DMA channel. Each individual DMAcapable peripheral has one or more dedicated DMA channels. For adescription of each DMA sequence, the DMA controller uses a set ofparameters—called a DMA descriptor. When successive DMA sequencesare needed, these descriptors can be linked or chained together. When1-16 ADSP-219x/2191 DSP Hardware Reference