ADSP-219x/2191 DSP Hardware Reference, Introduction

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ADSP-219x Architecture Overviewgenerate a 24-bit address for each bus. The DSP has three functions thatsupport access to the full memory map.• The DAGs generate 24-bit addresses for data fetches from the entireDSP memory address range. Because DAG index (address) registersare 16 bits wide and hold the lower 16-bits of the address, each ofthe DAGs has its own 8-bit page register (DMPGx) to hold the mostsignificant eight address bits. Before a DAG generates an address,the program must set the DAG’s DMPGx register to the appropriatememory page.• The program sequencer generates the addresses for instructionfetches. For relative addressing instructions, the program sequencerbases addresses for relative jumps, calls, and loops on the 24-bit ProgramCounter (PC). For direct addressing instructions (two-wordinstructions), the instruction provides an immediate 24-bit addressvalue. The PC allows linear addressing of the full 24 bit addressrange.• The program sequencer relies on an 8-bit Indirect Jump page (IJPG)register to supply the most significant eight address bits for indirectjumps and calls that use a 16-bit DAG address register for part ofthe branch address. Before a cross page jump or call, the programmust set the program sequencer’s IJPG register to the appropriatememory page.The ADSP-2191 has 1K word of on-chip ROM that holds boot routines.If peripheral booting is selected, the DSP starts executing instructionsfrom the on-chip boot ROM, which starts the boot process from theselected peripheral. For more information, see “Booting Modes” on page1-21. The on-chip boot ROM is located on Page 255 in the DSP’s memorymap.The ADSP-2191 has internal I/O memory for peripheral control and statusregisters. For more information, see the I/O memory space discussionon page 1-15.1-14 ADSP-219x/2191 DSP Hardware Reference
IntroductionExternal (Off-chip) MemoryEach of the ADSP-2191’s off-chip memory spaces has a separate controlregister, so applications can configure unique access parameters for eachspace. The access parameters include read and write wait counts, waitstatecompletion mode, I/O clock divide ratio, write hold time extension,strobe polarity, and data bus width. The core clock and peripheral clockratios influence the external memory access strobe widths. For more information,see “Clock Signals” on page 1-20. The off-chip memory spacesare:• External memory space (MS3-0 pins)• I/O memory space (IOMS pin)• Boot memory space (BMS pin)All of these off-chip memory spaces are accessible through the externalport, which can be configured for 8-bit or 16-bit data widths.External Memory Space. External memory space consists of four memorybanks. These banks can contain a configurable number of 64K wordpages. At reset, the page boundaries for external memory have Bank 0 containingpages 1−63, Bank 1 containing pages 64−127, Bank 2 containingpages 128−191, and Bank 3 containing pages 192−254. The MS3-0 memorybank pins select Bank 3-0, respectively. The external memory interfacedecodes the eight MSBs of the DSP program address to select one of thefour banks. Both the DSP core and DMA-capable peripherals can accessthe DSP’s external memory space.I/O Memory Space. The ADSP-2191 supports an additional externalmemory called I/O memory space. This space is designed to support simpleconnections to peripherals (such as data converters and externalregisters) or to bus interface ASIC data registers. I/O space supports a totalof 256K locations. The first 8K addresses are reserved for on-chip peripherals.The upper 248K addresses are available for external peripheraldevices and are selected with the IOMS pin. The DSP’s instruction set pro-ADSP-219x/2191 DSP Hardware Reference 1-15
Page 1 and 2: 1 INTRODUCTIONFigure 1-0.Table 1-0.
Page 3 and 4: IntroductionFigure 1-1 shows a deta
Page 5 and 6: IntroductionUnconstrained Data Flow
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Page 9 and 10: Introduction• Data Memory Address
Page 11 and 12: Introductioninterface to external m
Page 13: IntroductionBoth the DSP core and D
Page 17 and 18: Introductionchained, the completion
Page 19 and 20: Introductionthe SPI ports provide a
Page 21 and 22: IntroductionThe DSP provides a user
Page 23 and 24: Introductionory; and trace instruct
Page 25 and 26: Introductionand/or multifunction in
Page 27 and 28: IntroductionThe SV status condition
Page 29 and 30: IntroductionProgram Sequencer, Inst
Page 31 and 32: Introductionare available in ADSP-2
Page 33 and 34: Introduction• C Compiler and Libr

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