TigerSHARC DSP Hardware Specification, Revision 1.0.2, Link Ports

More documents

Recommendations

Info

Control Register (LCTLx)The checksum algorithm is:Checksum = B0 + B1 + … + B15 + C0 +C1 + … + C14where:B0, B1, etc. are byte1, byte2 …C0 is the Carry_out from B0 + B1,C1 is the Carry_out from B0 + B1 + B2 + C0,etc.C14 (the Carry_out from B0 + B1 + … + B15 + C0 + C1 + … + C13)is not added to the checksum.2. Time OutIf LxCLKIN is sampled low for a period of 256 cycles, a timeouterror has occurred. The RER[1] bit is set in the LSTATx register anda hardware interrupt is issued.If less than 16 bytes are received and LxCLKIN remains high for morethan four LxCLK cycles, the receiver does not detect a timeout error.The next quad word received overwrites the data in the receivebuffer.Control Register (LCTLx)The Control register programs every link port and contains control bitsunique to each one. There are four control registers—one for each linkport. The register is read/write.8 - 20 TigerSHARC DSP Hardware Specification
Link PortsLCTLx Register format76 5:3210PSIZELTENSPDVEREReserved31:12111098ReservedRTOELRENCERETTOETable 8-3. LCTLx Register Bit DescriptionsBit # Bit Description1:0 Reserved2 VERE Verification Enable5:3 SPD Transfer SpeedEnables checksum verification for received data, and creationof checksum on data transmission. Clear after reset.Defines the communication rate in which bytes are transmitted/received:1000… CCLK/8001… CCLK/4010… CCLK/3011… CCLK/21XX…ReservedThis field is clear after reset.6 LTEN Transmit EnableWhen cleared, any on-going transmit procedure inside theblock is ceased immediately, data are tri-stated. Any data thathave been written to the transmitter register before clearingLTEN, are cleared, and when setting LTEN again, the Transmitregister will be empty.Upon reset this bit is cleared.TigerSHARC DSP Hardware Specification 8 - 21
Page 1 and 2: 8 LINK PORTSFigure 8-0.Table 8-0.Li
Page 4 and 5: Link Architecturefrom the shift reg
Page 7 and 8: Link PortsThe interrupt can be used
Page 11 and 12: Link Ports3. One cycle after the tr
Page 14 and 15: Link Port Communication ProtocolThe
Page 16 and 17: Transmission DelaysAn example of a
Page 18 and 19: Error Detection Mechanismssenses th
Page 22 and 23: Control Register (LCTLx)Table 8-3.
Page 24: Status Register (LSTATx)Table 8-4.

TigerSHARC DSP Hardware Specification, Revision 1.0.2, Link Ports

Create successful ePaper yourself

Delete template?

Save as template?