TigerSHARC DSP Hardware Specification, Revision 1.0.2, Link Ports
TigerSHARC DSP Hardware Specification, Revision 1.0.2, Link Ports
TigerSHARC DSP Hardware Specification, Revision 1.0.2, Link Ports
You also want an ePaper? Increase the reach of your titles
YUMPU automatically turns print PDFs into web optimized ePapers that Google loves.
<strong>Link</strong> <strong>Ports</strong>Table 8-2. <strong>Link</strong> Port Register (Continued)Reg 0x2 LCTL2 <strong>Link</strong> # 2 control register 0x1804E2 Reset value:0x400(LREN=1)Reg 0x3 LCTL3 <strong>Link</strong> # 3 control register 0x1804E3 Reset value:0x400(LREN=1)Reg 0x10 LSTAT0 <strong>Link</strong> # 0 status register 0x1804F0 Read onlyReg 0x11 LSTAT1 <strong>Link</strong> # 1 status register 0x1804F1 Read onlyReg 0x12 LSTAT2 <strong>Link</strong> # 2 status register 0x1804F2 Read onlyReg 0x13 LSTAT3 <strong>Link</strong> # 3 status register 0x1804F3 Read onlyReg 0x18 LSTATC0 <strong>Link</strong> # 0 status clear registerReg 0x19 LSTATC1 <strong>Link</strong> # 1 status clear registerReg 0x1A LSTATC2 <strong>Link</strong> # 2 status clear registerReg 0x1B LSTATC3 <strong>Link</strong> # 3 status clear register0x1804F80x1804F90x1804FA0x1804FBRead onlyRead onlyRead onlyRead onlyDMAEach link port is associated with two DMA channels. One channel is usedfor transmitting data while the other is used for receiving data. The twoDMA channels can interface with either internal or external memory.<strong>TigerSHARC</strong> <strong>DSP</strong> <strong>Hardware</strong> <strong>Specification</strong> 8 - 5
Change language