Design and technology of DEPFET pixel sensors for ... - MPG HLL

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4Asourcedrain_1gate_2clearclear gateAclear gatedrain_2gate_1P+ implantN+ implantPolySilicon_1PolySilicon_2Contact_1Contact_2Metal_1Metal_2Fig.4: Layout example for a linear double pixel cell. Each whiterectangle surrounds a DEPMOS.For larger area sensor arrays, the availability ofmore than one metal layer is mandatory due to thenecessity of the row- and column-wise connectionsof the pixels. At the Semiconductor Laboratory of theMax-Planck-Institutes, a 150mm silicon technologyfor MOS type DEPFETs on high ohmic substrateswith two polysilicon and two metal layers has beendeveloped. Using the two polysilicon layers, linearDEPMOS transistors can be fabricated whereby thefirst polysilicon forms a lateral isolation frame andthe second one is used for the external gate of theDEPFET. This approach is different from that used incommon MOS technologies, where the lateraltransistor isolation is provided by locally oxidizedfield regions or shallow trenches filled with oxide.The channel isolation structure of the DEPFETs mustnot collect signal electrons and has to accomplish theintegration of the clear contacts.Fig.5: Potential distribution across the section A-A in Fig.4during the clear operation simulated with the 3D-Poisson solverPoseidon [18] (VClear = 20V, VBack = -30V, VSource = 0V,VDrain = -5V, VGate = -3V, VClear-Gate = 1V).The n+ doped clear region is close-by the internalgate, separated only by the first polysilicon layer. Inthe Collect and Read modes, the region underneaththe polysilicon acts as a potential barrier between theclear region and the internal gate. The barrier has tobe overcome during the Clear cycle when the clearcontact gets positive. The first polysilicon acts notonly as an isolation frame but also as a reset (clear)gate. It is held at a constant potential or can beswitched in order to alleviate the clear process. Asshown in Fig.4, the linear cell geometry allows for avery compact pixel layout free from potential pocketswhere the signal charge could disappear (see alsoFig.6). In any case, the implanted drain, source andclear regions are shared by neighboring cells. In thisway a small pixel size is achievable even with ratherrelaxed lithographic requirements. This feature,which defines also the tolerable defect size in theprocess, is important concerning the yield of largearea detectors.We have started a production run on 6-inch waferscontaining prototype arrays of up to 128x64 pixelsfor high energy and astrophysical applications [13-15]. The smallest pixel cell size is presently30x20µm².
54. Device simulationsTwo and three dimensional simulation tools [16-19] are used to optimize the layout and thetechnology parameters. Fig.6 shows the simulatedpotential distribution (section A-A in Fig.4) duringthe clear operation.Internal GateSourceClearDrainswitching on the external gate the device current isread out. The drain current response to a given signalcharge defines the amplification of the internal gateg q = ♎ I D /♎ q. To analyze the signal response of theDEPFET, 1600 electron-hole pairs were introducedby a locally and temporally limited increase of theShockley-Read-Hall generation rate using the twodimensional device simulator TeSCA [16]. Thesimulated signal response, shown in Fig.7,demonstrates an amplification potential of more than1nA per electron for optimized DEPFET structures.Fig.7: Simulated signal response to a signal charge generation of1600 electron-hole pairs.Fig.6: Potential distribution of a 2x4 array section parallel to thesurface at a depth of z=1µm during charge collection simulatedwith Poseidon (VClear = 3V, VBack = -25V, VSource = 0V,VDrain = -5V, VGate = 2V, VClear-Gate = 1V). A single cell ismarked by the dashed line.The simulation illustrates that the electrons canflow unopposed from the internal gate into the clearcontact. The applied clear voltage of 20V can bereduced by lowering the potential barrier in the cleargate region. During charge collection, the transistor isswitched off and the potential of the internal gate canbe adjusted by the voltage of the external gate viacapacitive coupling. Fig.6 shows the potential at adepth of 1µm, as seen by drifting electrons generatedin the bulk. Note that there is not any attraction of then+ clear contact to the electrons at this depth. This isthe result of the negative space charge of a deepboron doping implanted beneath the clear region. By5. Thinning technologyThe DEPFET, as a fully depleted device, needs, inaddition to the front side structures, a p+n diode atthe backside. Therefore a standard thinning process isnot applicable because it would destroy the backsidepn – junctions. The key technology of the processsequence illustrated in Fig.8 is the direct waferbonding [20]. It starts with a sensor wafer on top anda handle wafer on bottom, which are bonded togetheron their oxidized surfaces (Fig.8 a). The top wafer,which already contains the backside p+implantations, is thinned to a thickness of ~50µm bystandard wafer grinding and polishing (Fig.8 b). Thisside is where the actual device is fabricated. Duringthe front side fabrication process, the obtainedsandwich package can be handled like a standard
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