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Design and technology of DEPFET pixel sensors for ... - MPG HLL

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6wafer without special precautions <strong>for</strong> backsideprotection (Fig.8 c). After topside metallization <strong>and</strong>passivation, the h<strong>and</strong>le wafer is partially etched back(Fig.8 d) leaving a small frame large enough toprovide mechanical stability <strong>and</strong> space <strong>for</strong> the affixedsteering <strong>and</strong> readout chips [5].Fig.9: First results <strong>of</strong> the thinning <strong>technology</strong> development -mechanical samples. The size <strong>of</strong> the upper part is 800x104mm².6. SummaryFig.8 a-d: Joint process sequence <strong>of</strong> wafer thinning <strong>and</strong><strong>DEPFET</strong> production.An inherent advantage <strong>of</strong> this <strong>technology</strong> is thatthe inner silicon oxide acts as a stop layer <strong>for</strong> theetchant, leaving the backside diode <strong>of</strong> the sensorwafer unaffected by the etching. With the proposedconcept, the material budget per layer can be reducedto the range <strong>of</strong> 0.1-0.15% <strong>of</strong> a radiation length,including the already thinned read out <strong>and</strong> line driverchips. Pictures <strong>of</strong> the first mechanical samplesproduced with this <strong>technology</strong> are shown in Fig.9.The <strong>DEPFET</strong> is a promising c<strong>and</strong>idate to fulfillthe challenging detector requirements <strong>of</strong> future highenergy physics experiments, e.g. the TESLA vertexdetector. It <strong>of</strong>fers excellent low noise per<strong>for</strong>mance atroom temperature. Thus the <strong>DEPFET</strong> has thepotential to achieve a good spatial resolution <strong>and</strong> afast readout speed even on a thinned detectorsubstrate. The overall requirement <strong>of</strong> a minimummaterial budget is addressed by an intrinsically lowpower consumption, thereby saving material <strong>for</strong>cooling structures. At the MPI SemiconductorLaboratory, a new MOS based <strong>technology</strong> on 150mmwafer has been developed to produce large detectorarrays.Linearly shaped <strong>DEPFET</strong>s <strong>of</strong> a size <strong>of</strong> about25x25µm² can be made by using two polysiliconlayers. As a detector <strong>pixel</strong> cell consists <strong>of</strong> only onesingle <strong>DEPFET</strong> transistor, it can be produced byrather large lithographic structures with minimumsize <strong>of</strong> 2µm. There<strong>for</strong>e the yield problem occurringespecially in large area detectors is expected to berelaxed. Technology development <strong>and</strong> detectordesign based on two <strong>and</strong> three dimensional processes<strong>and</strong> device simulations demonstrating the operation<strong>and</strong> the technological feasibility <strong>of</strong> <strong>DEPFET</strong> arrays.The first production run has been started. A thinning<strong>technology</strong> based on direct wafer bonding isproposed. Mechanical samples with 50µm thinnedregions were fabricated successfully.

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