Help You to Win! C*Core's Scalable Design Platform - Power.org

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C*Core SoC Design Platform• C*Core C9000– High-performance (2.5 DMIPS/MHz ), Out-of-Order, 5-issue / 9-pipeline superscalar RISC CPU– Integrated floating-point unit– L1 caches that support cache coherency in SMP systems– Tightly coupled to an L2 cache controller that supports coherency managementThe Power Architecture and Power.org word marks and the Power and Power.org logos and related marks are trademarks and service marks licensed by Power.org.
C*Core SoC Design Platform• IPs in CSOC9000 Platform– CPU• C9000– Operating System• Android 2.3 /Linux 2.6.3x, Support Adobe Flash Player 10.3.– HD Video• 4Ch 1080P Encode and Decode, Support AVS, Google WebM videoformat– On Chip DDR2/3 SRAM Controller– HD Audio• DTS-HD 7.1 Master Audio, Dolby 7.1 TrueHD, and DSP is integrated– 2D/3D GPU• Support OPENGL ES 2.0 and OPEN VG 1.1.– Wireless• Wi-Fi, Bluetooth, 3G,GPS baseband– Display• 2048xN TFT panel muti-point touch panel– Interface• PCIe/USB/HDMI /SATAII/LVDS/TV CVBS/• Ethernet 10/100/1000 Mbps, full-duplex MACsThe Power Architecture and Power.org word marks and the Power and Power.org logos and related marks are trademarks and service marks licensed by Power.org.
Page 7 and 8: C*Core CPU Road MapThe Power Archit
Page 9 and 10: C*Core Business ModelThe Power Arch
Page 11 and 12: Business Model of C*Core• Provide
Page 13: PLBC*Core SoC Design Platform• C*
Page 17 and 18: C*Core SoC Design Platform• C*Cor
Page 19 and 20: C*Core SoC Design Platform• IPs i
Page 25 and 26: C*Core SoC Design Platform• IPs i
Page 27 and 28: C*Core SoC Design Platform• Suppo
Page 29 and 30: C*Core SoC Design Platform ( exampl
Page 31 and 32: Information Security SoC Based on C
Page 33 and 34: Touch Panel Controller Based on C*C
Page 35 and 36: Summary• C*Core can provide a ser

Help You to Win! C*Core's Scalable Design Platform - Power.org

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