Help You to Win! C*Core's Scalable Design Platform - Power.org
Help You to Win! C*Core's Scalable Design Platform - Power.org
Help You to Win! C*Core's Scalable Design Platform - Power.org
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C*Core SoC <strong>Design</strong> <strong>Platform</strong>• C*Core C2000Features– Five-stage 32-bit singleissuepipeline– 32 General PurposeRegisters (GPR)/Staticbranch prediction– MMU with a 64-entryI-PortI-OCMBus InterfaceCacheI-CacheControllerMMUShadowITLBC2000PLB/AHB Master WrapperInstructionCacheUnifiedTLBDataCacheD-CacheControllerShadowDTLBD-PortD-OCM– Separate instruction anddata L1 caches, withconfigurable size– 1.52 DMIPS/MHzAPUCPUInstruction UnitPre-fetchBuffersDecoderExecute UnitALU32 GPRsMACDCR– Support PLB4/AXI/AHB/OCM/DCR bus pro<strong>to</strong>calsJTAGTraceFacilitiesDebugUnitTimersPIT FIT WatchdogInterruptUnitInterruptsThe <strong>Power</strong> Architecture and <strong>Power</strong>.<strong>org</strong> word marks and the <strong>Power</strong> and <strong>Power</strong>.<strong>org</strong> logos and related marks are trademarks and service marks licensed by <strong>Power</strong>.<strong>org</strong>.