ISE Design Suite Software Manuals and Help - Xilinx

: ISE Design Suite Software Manuals and Help - PDF CollectionTitleDesign Entry (Cont.)SummaryISE Text Editor Help • The ISE Text Editor lets you create, view, and edit text files,such as ASCII, UCF, VHDL, Verilog, and TCL files.ISim User Guide• ISE Text Editor Help is now part of ISE HelpDescribes the ISE simulator that lets you perform functional andtiming simulations for VHDL, Verilog and mixed VHDL/VerilogdesignsLibraries Guides • Includes Xilinx® Unified Library information arrangedalphabetically and by functional categoriesPACE Help• Describes each Xilinx design element, includingarchitectures, usage information, syntax examples, andrelated constraintsDescribes how to use the Pinout and Area Constraints Editor(PACE) to define legal pin assignments and to create properlysized area constraints for CPLD devices.Note PACE is for use with CPLD devices only. For pinassignment in FPGA Devices, see the PlanAhead User GuidePlanAhead User Guide • Provides detailed information about the PlanAheadsoftwareSchematic and SymbolEditors Help• Describes the I/O pin planning used in pre-synthesis andpost-synthesis using the PinAhead environment in ProjectNavigator• Describes a floorplanning methodology for bothpost-synthesis and post-implementation that allowsdesigners to constrain critical logic to obtain shorterinterconnect lengths with less delay• For more information on PlanAhead, seehttp://www.xilinx.com/tools/planahead.htm• Describes how to use the Schematic Editor to create a toplevel schematic as input for the Behavioral Simulationor Synthesis steps in the ISE® design flow, and how tocreate lower-level schematics to instantiate in this top-levelschematic.• Describes how to create a new symbol or edit an existingsymbol to instantiate in a schematic.• Schematic and Symbol Editors Help is now part of ISE HelpSystem Generator for DSP • Describes the System Generator DSP developmentenvironments; MATLAB® and Simulink®Timing Constraints UserGuide• Describes how to design, simulate, implement and debughigh performance FPGA-based DSP systemsDescribes a timing constraint methodology to address timingclosure for high-performance applicationsISE Design Suite Software Manuals and Help4 www.xilinx.com UG681(v 12.1) April 19, 2010