Xilinx UG075 Virtex-4 FPGA Packaging and Pinout Specification ...

RXilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the developmentof designs to operate with Xilinx hardware devices. You may not reproduce, distribute, republish, download, display, post, or transmit theDocumentation in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise,without the prior written consent of Xilinx. Xilinx expressly disclaims any liability arising out of your use of the Documentation. Xilinx reservesthe right, at its sole discretion, to change the Documentation without notice at any time. Xilinx assumes no obligation to correct any errorscontained in the Documentation, or to advise you of any corrections or updates. Xilinx expressly disclaims any liability in connection withtechnical support or assistance that may be provided to you in connection with the Information.THE DOCUMENTATION IS DISCLOSED TO YOU “AS-IS” WITH NO WARRANTY OF ANY KIND. XILINX MAKES NO OTHERWARRANTIES, WHETHER EXPRESS, IMPLIED, OR STATUTORY, REGARDING THE DOCUMENTATION, INCLUDING ANYWARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NONINFRINGEMENT OF THIRD-PARTYRIGHTS. IN NO EVENT WILL XILINX BE LIABLE FOR ANY CONSEQUENTIAL, INDIRECT, EXEMPLARY, SPECIAL, OR INCIDENTALDAMAGES, INCLUDING ANY LOSS OF DATA OR LOST PROFITS, ARISING FROM YOUR USE OF THE DOCUMENTATION.© 2004-2008 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE and other designated brands included herein are trademarks of Xilinxin the United States and other countries. The PowerPC name and logo are registered trademarks of IBM Corp. and used under license. Allother trademarks are the property of their respective owners.Revision HistoryThe following table shows the revision history for this document.VersionRevision08/02/04 1.0 Initial Xilinx release. (Printed Handbook version.)09/03/04 1.1 Added Chapters 2 and 3.10/05/04 1.2 Removed FF1152 package information from Chapters 2 and 3.11/05/04 1.3 Added FF1152 pinout information, and revised TDN, TDP, ADC, and SM pin references.11/30/04 2.0 • Revised four pins affecting only XC4VFX100 devices in the FF1152 package.• Added FF676 pinout information.• Corrected symbol used for pin AN28 in the FF1513 pinout diagram.• Added MGT pin definitions to Table 1-3.12/21/04 2.1 • Changed four VCCO pins to No Connects in Banks 9 and 10, affecting onlyXC4VFX20 devices in the FF672 package.• Added a colorized SelectIO and bank information diagram for each package.• Made minor changes to pin definitions in Table 1-3.01/19/05 2.2 • Corrected pin A9 in the FF1152 package (Table 2-6), affecting only XC4VFX100devices.• Corrected the FF1152 pinout diagrams.02/10/05 2.3 • Removed FF676 package information from the guide.• Made minor changes to pin definitions in Table 1-3.Virtex-4 FPGA Packaging and Pinout Specification www.xilinx.com UG075 (v3.3) September 19, 2008

arrangements should bring exposures into compliance in a structured and orderly mannerwhile keeping payments sustainable.4. Appropriate accounting, reporting, and disclosure of troubled debt restructurings.Management should review end-of-draw modifications for appropriate identification ofTDRs and accrual status. TDR treatment is appropriate when a lender grants a concession toa borrower that it would not otherwise consider because of the borrower’s financialdifficulties. 10 Financial difficulties can include the probable inability of a borrower to meetthe loan terms, assuming no modification takes place when the borrower is facing ascheduled balloon payment at maturity or the payment shock associated with a contractualincrease in the monthly payments.5. Appropriate segmentation and analysis of end-of-draw exposure in allowance for loanand lease losses (ALLL) estimation processes. Estimates of the ALLL, including TDRimpairment estimates, should consider the impact of payment shock and loss of lineavailability associated with the end-of-draw period. In accordance with the “InteragencyJunior Lien Allowance Guidance,” HELOCs approaching their end-of-draw periods should,when volumes warrant, generally be a separate portfolio segment in the ALLL estimationprocess. Before significant HELOC volumes reach their end-of-draw periods, managementshould be capturing information and preparing analyses that clarify the nature and magnitudeof exposures.End-of-Draw Risk Management ExpectationsManagement should implement policies and procedures for managing HELOCs nearing theirend-of-draw periods that are commensurate with the size and complexity of the portfolio.Prudent risk management expectations generally include:1. Developing a clear picture of scheduled end-of-draw period exposures. Managementreports should provide a clear understanding of end-of-draw exposures and identify higherrisksegments of the portfolio. Management reports should also identify contractual drawperiod transition dates for all HELOCs, showing maturity schedules in the aggregate and bysignificant segments of performing and non-performing borrowers (including distinguishingbetween performing borrowers that are higher risk and those that are not). Segments typicallyinclude product types, post-draw payment characteristics (such as interest-only payments,balloon payments, and amortization periods), origination channels (such as retail, broker,correspondent, and mergers), or borrower characteristics (such as credit score bands andutilization rates) where performance may vary. Refer to the Interagency Junior LienAllowance Guidance for further information on account and portfolio management.Additional analyses that include expected payoffs, attrition, utilization rates, delinquency ormodification status of associated first liens, 11 or other factors that might change risk levelsbefore contractual end-of-draw periods may also be helpful to assess risk. For example, preend-of-drawpayment history for a borrower may indicate that contractual payment shockwill have a limited effect on that borrower if the payments made have consistently exceednfloating.• Table 2-7: Corrected note callout on AVDD_ADC (pin B22) to (3).• Chapter 6: Deleted section “Virtex-4 LX, SX, and FX Device Marking.”05/29/08 3.2 • Table 1-3: Rephrased last sentence of PWRDWN_B_0 description, describing how toconnect this signal.• Figure 3-14, page 256: Corrected symbols for AE16 and AG16 in pinout diagram.• Figure 4-1, page 270: Updated drawing, including JEDEC specification in Note 3.• Updated “References,” page 284.09/19/08 3.3 • Figure 3-14, page 256: Corrected symbol for AG16 in pinout diagram.UG075 (v3.3) September 19, 2008 www.xilinx.com Virtex-4 FPGA Packaging and Pinout Specification

Virtex-4 FPGA Packaging and Pinout Specification www.xilinx.com UG075 (v3.3) September 19, 2008

RFF676 Package Pinout Diagram (LX25) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254FF676 Color-Coded SelectIO and Bank Information. . . . . . . . . . . . . . . . . . . . . . . . . 255FF1148 Package Pinout Diagram (LX40, LX60, and SX55) . . . . . . . . . . . . . . . . . . . . 256FF1148 Package Pinout Diagram (LX80, LX100, and LX160) . . . . . . . . . . . . . . . . . . 257FF1148 Color-Coded SelectIO and Bank Information. . . . . . . . . . . . . . . . . . . . . . . . 258FF1152 Package Pinout Diagram (FX40) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259FF1152 Package Pinout Diagram (FX60) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260FF1152 Package Pinout Diagram (FX100) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261FF1152 Color-Coded SelectIO and Bank Information. . . . . . . . . . . . . . . . . . . . . . . . 262FF1513 Package Pinout Diagram (LX100, LX160, and LX200) . . . . . . . . . . . . . . . . . 263FF1513 Color-Coded SelectIO and Bank Information. . . . . . . . . . . . . . . . . . . . . . . . 264FF1517 Package Pinout Diagram (FX100) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265FF1517 Package Pinout Diagram (FX140) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266FF1517 Color-Coded SelectIO and Bank Information. . . . . . . . . . . . . . . . . . . . . . . . 267Chapter 4: Mechanical DrawingsSummary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269SF363 Flip-Chip Fine-Pitch BGA Package Specifications (0.80 mm pitch) . . . . . . . . 270FF668 Flip-Chip Fine-Pitch BGA Package Specifications (1.00 mm pitch) . . . . . . . . 271FF672 Flip-Chip Fine-Pitch BGA Package Specifications (1.00 mm pitch) . . . . . . . . 272FF676 Flip-Chip Fine-Pitch BGA Package Specifications (1.00 mm pitch) . . . . . . . . 273FF1148 Flip-Chip Fine-Pitch BGA Package Specifications (1.00 mm pitch) . . . . . . . 274FF1152 Flip-Chip Fine-Pitch BGA Package Specifications (1.00 mm pitch) . . . . . . . 275FF1513 Flip-Chip Fine-Pitch BGA Package Specifications (1.00 mm pitch) . . . . . . . 276FF1517 Flip-Chip Fine-Pitch BGA Package Specifications (1.00 mm pitch) . . . . . . . 277Chapter 5: Thermal SpecificationsSummary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279Virtex-4 FPGA Power Management Strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281Some Thermal Management Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282Support for Compact Thermal Models (CTM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284Chapter 6: Package MarkingVirtex-4 Device Package Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2856 www.xilinx.com Virtex-4 FPGA Packaging and Pinout SpecificationUG075 (v3.3) September 19, 2008

RPrefaceAbout This GuideOrganization of This GuideRelated DocumentationThis guide describes Virtex ® -4 device pinouts and package specifications; it also includespinout diagrams and thermal data.This document is comprised of the following chapters:• Chapter 1, “Packaging Overview”Provides an introduction to the Virtex-4 family with a summary of maximum I/Osavailable in each device/package combination. Also includes table of pin definitions.• Chapter 2, “Pinout Tables”Provides pinout information for all Virtex-4 devices and packages.• Chapter 3, “Pinout Diagrams”Provides pinout diagrams for all Virtex-4 package/device combinations.• Chapter 4, “Mechanical Drawings”Provides mechanical drawings of all Virtex-4 FPGA packages.• Chapter 5, “Thermal Specifications”Provides thermal data associated with Virtex-4 FPGA packages. Discusses powermanagement strategy and thermal management options for Virtex-4 FPGAs.• Chapter 6, “Package Marking”Defines the markings on Virtex-4 FPGA packages.The following documents are also available for download at http://www.xilinx.com/virtex4.• Virtex-4 Family OverviewThe features and product selection of the Virtex-4 family are outlined in this overview.• Virtex-4 FPGA Data Sheet: DC and Switching CharacteristicsThis data sheet contains the DC and Switching Characteristic specifications for theVirtex-4 family.• Virtex-4 FPGA User GuideChapters in this guide cover the following topics:- Clocking ResourcesVirtex-4 FPGA Packaging and Pinout Specification www.xilinx.com 7UG075 (v3.3) September 19, 2008

Preface: About This GuideRAdditional Resources- Digital Clock Manager (DCM)- Phase-Matched Clock Dividers (PMCD)- Block RAM and FIFO memory- Configurable Logic Blocks (CLBs)- SelectIO Resources- SelectIO Logic Resources- Advanced SelectIO Logic Resources• XtremeDSP for Virtex-4 FPGAs User GuideThis guide describes the XtremeDSP slice and includes reference designs for usingDSP48 math functions and various FIR filters.• Virtex-4 FPGA Configuration GuideThis all-encompassing configuration guide includes chapters on configurationinterfaces (serial and SelectMAP), bitstream encryption, Boundary-Scan and JTAGconfiguration, reconfiguration techniques, and readback through the SelectMAP andJTAG interfaces.• Virtex-4 PCB Designer’s GuideThis designer’s guide provides information on the design of PCBs for Virtex-4 devices.It considers all aspects of the PCB from the system level down to the minute details.This guide focuses on strategies for making design decisions at the PCB and interfacelevel.• Virtex-4 RocketIO Multi-Gigabit Transceiver User GuideThis guide describes the RocketIO Multi-Gigabit Transceivers available in theVirtex-4 FX family.• Virtex-4 FPGA Embedded Tri-Mode Ethernet MAC User GuideThis guide describes the Tri-Mode Ethernet Media Access Controller available in theVirtex-4 FX family.• PowerPC 405 Processor Block Reference GuideThis guide is updated to include the PowerPC ® 405 processor block available in theVirtex-4 FX family.To search the database of silicon and software questions and answers, or to create atechnical support case in WebCase, visit the following Xilinx website:http://www.xilinx.com/support8 www.xilinx.com Virtex-4 FPGA Packaging and Pinout SpecificationUG075 (v3.3) September 19, 2008

RTypographical ConventionsTypographical ConventionsThe following typographical conventions are used in this document:Convention Meaning or Use ExampleItalic fontReferences to other documentsEmphasis in textSee the Virtex-4 ConfigurationGuide for more information.The address (F) is asserted afterclock event 2.Underlined Text Indicates a link to a web page. http://www.xilinx.com/virtex4Virtex-4 FPGA Packaging and Pinout Specification www.xilinx.com 9UG075 (v3.3) September 19, 2008

Preface: About This GuideR10 www.xilinx.com Virtex-4 FPGA Packaging and Pinout SpecificationUG075 (v3.3) September 19, 2008

RChapter 1Packaging OverviewSummaryIntroductionThis chapter covers the following topics:• Introduction• Device/Package Combinations and Maximum I/Os• Pin DefinitionsThis section describes the pinouts for Virtex-4 devices in the 0.80 mm and 1.00 mm pitchflip-chip fine-pitch BGA packages.Virtex-4 devices are offered exclusively in high performance flip-chip BGA packages thatare optimally designed for improved signal integrity and jitter. Package inductance isminimized as a result of optimal placement and even distribution, as well as an increasednumber, of Power and GND pins.All of the devices supported in a particular package are pinout compatible and are listed inthe same table (one table per package). Pins that are not available for the smaller devicesare listed in the “No Connects” column of each table. VCCO_# pins listed as “NoConnects” can be required for larger devices. This must be considered when migrating intoa larger part within the same package.Each device is split into eight or more I/O banks to allow for flexibility in the choice of I/Ostandards (see the Virtex-4 FPGA User Guide). Global pins, including JTAG, configuration,and power/ground pins, are listed at the end of each table. Table 1-3 provides definitionsfor all pin types.For the very latest Virtex-4 FPGA pinout information, visit www.xilinx.com and check forany updates to this document.Virtex-4 FPGA Packaging and Pinout Specification www.xilinx.com 11UG075 (v3.3) September 19, 2008

Chapter 1: Packaging OverviewRDevice/Package Combinations and Maximum I/OsTable 1-1: Flip-Chip PackagesTable 1-1 shows the maximum number of user I/Os possible in Virtex-4 FPGA flip-chippackages.• SF denotes flip-chip fine-pitch BGA (0.80 mm pitch)• FF denotes flip-chip fine-pitch BGA (1.00 mm pitch)Package SF363 FF668 FF672 FF676 FF1148 FF1152 FF1513 FF1517Pitch (mm) 0.80 mm 1.00 mm 1.00 mm 1.00 mm 1.00 mm 1.00 mm 1.00 mm 1.00 mmSize (mm) 17 x 17 27 x 27 27 x 27 27 x 27 35 x 35 35 x 35 40 x 40 40 x 40Maximum I/Os 240 448 352 448 768 576 960 768Table 1-2 shows the number of available I/Os, the number of RocketIO multi-gigabittransceivers (MGTs), and the number of differential I/O pairs for each Virtex-4 XC4VLX,XC4VSX, and XC4VFX device/package combination. The number of I/Os per packageincludes all user I/Os except the fifteen control pins (CCLK, DONE, M0, M1, M2, PROG_B,PWRDWN_B, TCK, TDI, TDO, TMS, HSWAPEN, DXN, DXP, AND RSVD) and theRocketIO MGT pins (AVCCAUXTX, AVCCAUXRX, AVCCAUXMGT, TXP, TXN, RXP,RXN, VTTX, VTRX, MGTCLK, MGTVREF, RTERM, and GNDA).Table 1-2: Virtex-4 FPGA Available I/Os and RocketIO MGT Pins per Device/Package CombinationVirtex-4DeviceUser I/Os &RocketIO MGT PinsVirtex-4 FPGA PackageSF363 FF668 FF672 FF676 FF1148 FF1152 FF1513 FF1517Available User I/Os 240 320 - 320 - - - -XC4VLX15RocketIO Transceivers N/A N/A - N/A - - - -Differential I/O Pairs 120 160 - 160 - - - -Available User I/Os 240 448 - 448 - - - -XC4VLX25RocketIO Transceivers N/A N/A - N/A - - - -Differential I/O Pairs 120 224 - 224 - - - -Available User I/Os - 448 - 640 - - -XC4VLX40RocketIO Transceivers - N/A - N/A - - -Differential I/O Pairs - 224 - 320 - - -Available User I/Os - 448 - 640 - - -XC4VLX60RocketIO Transceivers - N/A - N/A - - -Differential I/O Pairs - 224 - 320 - - -Available User I/Os - - - 768 - - -XC4VLX80RocketIO Transceivers - - - N/A - - -Differential I/O Pairs - - - 384 - - -12 www.xilinx.com Virtex-4 FPGA Packaging and Pinout SpecificationUG075 (v3.3) September 19, 2008

RDevice/Package Combinations and Maximum I/OsTable 1-2: Virtex-4 FPGA Available I/Os and RocketIO MGT Pins per Device/Package Combination (Continued)Virtex-4DeviceUser I/Os &RocketIO MGT PinsVirtex-4 FPGA PackageSF363 FF668 FF672 FF676 FF1148 FF1152 FF1513 FF1517Available User I/Os - - - 768 - 960 -XC4VLX100RocketIO Transceivers - - - N/A - N/A -Differential I/O Pairs - - - 384 - 480 -Available User I/Os - - - 768 - 960 -XC4VLX160RocketIO Transceivers - - - N/A - N/A -Differential I/O Pairs - - - 384 - 480 -Available User I/Os - - - - - 960 -XC4VLX200RocketIO Transceivers - - - - - N/A -Differential I/O Pairs - - - - - 480 -Available User I/Os - 320 - - - - - -XC4VSX25RocketIO Transceivers - N/A - - - - -Differential I/O Pairs - 160 - - - - -Available User I/Os - 448 - - - - -XC4VSX35RocketIO Transceivers - N/A - - - - -Differential I/O Pairs - 224 - - - - -Available User I/Os - - - 640 - - -XC4VSX55RocketIO Transceivers - - - N/A - - -Differential I/O Pairs - - - 320 - - -Available User I/Os 240 320 - - - - -XC4VFX12RocketIO Transceivers N/A N/A - - - - -Differential I/O Pairs 120 160 - - - - - -Available User I/Os - - 320 - - - - -XC4VFX20RocketIO Transceivers - - 8 - - - - -Differential I/O Pairs - - 160 - - - - -Available User I/Os - - 352 - - 448 - -XC4VFX40RocketIO Transceivers - - 12 - - 12 - -Differential I/O Pairs - - 176 - - 224 - -Available User I/Os - - 352 - - 576 - -XC4VFX60RocketIO Transceivers - - 12 - - 16 - -Differential I/O Pairs - - 176 - - 288 - -Virtex-4 FPGA Packaging and Pinout Specification www.xilinx.com 13UG075 (v3.3) September 19, 2008

Chapter 1: Packaging OverviewRTable 1-2: Virtex-4 FPGA Available I/Os and RocketIO MGT Pins per Device/Package Combination (Continued)Virtex-4DeviceUser I/Os &RocketIO MGT PinsVirtex-4 FPGA PackageSF363 FF668 FF672 FF676 FF1148 FF1152 FF1513 FF1517Available User I/Os - - - - 576 - 768XC4VFX100RocketIO Transceivers - - - - 20 - 20Differential I/O Pairs - - - - 288 - 384Available User I/Os - - - - - - 768XC4VFX140RocketIO Transceivers - - - - - - 24Differential I/O Pairs - - - - - - 384Pin DefinitionsTable 1-3 provides a description of each pin type listed in Virtex-4 FPGA pinout tables. The“_#” suffix appended to some pin descriptions indicates the bank in which that pin resides.Pins that do not have this suffix appended are not associated with any particular bank. Fora description of RocketIO transceiver pins, see the Virtex-4 RocketIO Multi-GigabitTransceiver User Guide (UG076).Table 1-3: Virtex-4 FPGA Pin DefinitionsPin Name Direction DescriptionUser I/O PinsIO_LXXY_#Multi-Function PinsIO_LXXY_ZZZ_#Input/OutputAll user I/O pins are capable of differential signalling and can implementLVDS, LVDSEXT, ULVDS, BLVDS, LVPECL, or LDT pairs. Each user I/Ois labeled “IO_LXXY_#”, where:IO indicates a user I/O pin.LXXY indicates a differential pair, with XX a unique pair in the bankand Y = [P|N] for the positive/negative sides of the differential pair.Multi-function pins are labelled “IO_LXXY_ZZZ_#”, where ZZZrepresents one or more of the functions described below.For a given multi-function pin, ZZZ is one or more of the following:ADCnDnCC (2)GC (2)Input/OutputInput/OutputInput/OutputInput/OutputADC1 through ADC7 input pins are reserved for future use but can beused for I/O or other designated functions.In SelectMAP mode, D0 through D31 are configuration data pins. These pinsbecome user I/Os after configuration, unless the SelectMAP port is retained.These lower capacitance clock pins connect to Clock Capable I/Os. Thesepins do not support LVDS outputs, and they become regular user I/Oswhen not needed for clocks.These lower capacitance clock pins connect to Global Clock Buffers. Thesepins do not support LVDS outputs, and they become regular user I/Oswhen not needed for clocks. For single-ended clock inputs, use P-side pinsonly.14 www.xilinx.com Virtex-4 FPGA Packaging and Pinout SpecificationUG075 (v3.3) September 19, 2008

RPin DefinitionsTable 1-3: Virtex-4 FPGA Pin Definitions (Continued)Pin Name Direction DescriptionLC (2) Input/Output These lower capacitance pins do not support LVDS outputs.SMnV REFVRNVRPInput/OutputInput/OutputInput/OutputInput/OutputSM1 through SM7 input pins are reserved for future use but can be usedfor I/O or other designated functions.These are input threshold voltage pins. They become user I/Os when anexternal threshold voltage is not needed (per bank).This pin is for the DCI voltage reference resistor of N transistor (per bank,to be pulled High with reference resistor).This pin is for the DCI voltage reference resistor of P transistor (per bank,to be pulled Low with reference resistor).Dedicated Configuration Pins (1)CCLK_0Input/OutputConfiguration clock. Output and input in Master mode or Input in Slavemode.CS_B_0 Input In SelectMAP mode, this is the active-low Chip Select signal.D_IN_0 Input In bit-serial modes, D_IN is the single-data input.DONE_0DOUT_BUSY_0Input/OutputOutputDONE is a bidirectional signal with an optional internal pull-up resistor.As an output, this pin indicates completion of the configuration process.As an input, a Low level on DONE can be configured to delay the start-upsequence.In SelectMAP mode, BUSY controls the rate at which configuration data isloaded.In bit-serial modes, DOUT gives preamble and configuration data to downstreamdevices in a daisy chain.HSWAPEN Input Enable I/O pull-ups during configurationINIT_B_0Bidirectional(open-drain)When Low, this pin indicates that the configuration memory is beingcleared. When held Low, the start of configuration is delayed. Duringconfiguration, a Low on this output indicates that a configuration dataerror has occurred.M0_0, M1_0, M2_0 Input Configuration mode selectionPROG_B_0PWRDWN_B_0InputInput(unsupported)Active Low asynchronous reset to configuration logic. This pin has apermanent weak pull-up resistor.Active Low power-down pin (unsupported). Driving this pin Low canadversely affect device operation and configuration. PWRDWN_B is internallypulled High, which is its default state. It does not require an external pull-up.Do not connect this pin to GND; leave it floating or pull it up to V CC .RDWR_B_0 Input In SelectMAP mode, this is the active-low Write Enable signal.TCK_0 Input Boundary-Scan ClockTDI_0 Input Boundary-Scan Data InputTDO_0 Output Boundary-Scan Data OutputVirtex-4 FPGA Packaging and Pinout Specification www.xilinx.com 15UG075 (v3.3) September 19, 2008

Chapter 1: Packaging OverviewRTable 1-3: Virtex-4 FPGA Pin Definitions (Continued)Pin Name Direction DescriptionTMS_0 Input Boundary-Scan Mode SelectTDP_0, TDN_0 N/A Temperature-sensing diode pins (Anode: TDP, Cathode: TDN).Reserved PinsAVDD_SMInputThis pin is reserved and should be connected to 2.5V (sharing the samePCB supply distribution as V CCAUX is acceptable).AVSS_SM Input This pin is reserved for future use and should be connected to GND.VN_SM Input This pin is reserved for future use and should be connected to GND.VP_SM Input This pin is reserved for future use and should be connected to GND.VREFN_SM Input This pin is reserved for future use and should be connected to GND.VREFP_SM Input This pin is reserved for future use and should be connected to GND.AVDD_ADCInputThis pin is reserved and should be connected to 2.5V (sharing the samePCB supply distribution as V CCAUX is acceptable).AVSS_ADC Input This pin is reserved for future use and should be connected to GND.VN_ADC Input This pin is reserved for future use and should be connected to GND.VP_ADC Input This pin is reserved for future use and should be connected to GND.VREFN_ADC Input This pin is reserved for future use and should be connected to GND.VREFP_ADC Input This pin is reserved for future use and should be connected to GND.RSVD N/A Reserved pin - do not connectOther PinsGND Input Ground.V BATT_#InputDecryptor key memory backup supply. If unused, this pin should be tied toV CC or GND.V CCAUX Input Power-supply pins for auxiliary circuitsV CCINT Input Power-supply pins for the internal core logicV CCO_# Input Power-supply pins for the output drivers (per bank)RocketIO Multi-Gigabit Transceiver (MGT) PinsAVCCAUXRXA_#,AVCCAUXRXB_#InputAnalog power supply for receive circuitry of the RocketIO MGT (1.2V).AVCCAUXTX_# Input Analog power supply for transmit circuitry of the RocketIO MGT (1.2V).AVCCAUXMGT_# Input Analog power supply for global bias (2.5V).GNDA_# Input Ground for the analog circuitry of the RocketIO MGT.MGTCLK_# Input Differential reference clock for the RocketIO MGT.16 www.xilinx.com Virtex-4 FPGA Packaging and Pinout SpecificationUG075 (v3.3) September 19, 2008

RPin DefinitionsTable 1-3: Virtex-4 FPGA Pin Definitions (Continued)Pin Name Direction DescriptionRXPPADA_#,RXPPADB_#RXNPADA_#,RXNPADB_#TXPPADA_#,TXPPADB_#TXNPADA_#,TXNPADB_#VTRXA_#,VTRXB_#VTTXA_#,VTTXB_#InputInputOutputOutputInputInputPositive differential receive port of the RocketIO MGT.Negative differential receive port of the RocketIO MGT.Positive differential transmit port of the RocketIO MGT.Negative differential transmit port of the RocketIO MGT.Receive termination supply for the RocketIO MGT (0V - 2.5V).Transmit termination supply for the RocketIO MGT (1.2V - 1.5V).Notes:1. All dedicated pins (JTAG and configuration) are powered by V CC_CONFIG .2. For more information on lower capacitance pins, see the Virtex-4 User Guide (UG070).3. For more information on RocketIO transceiver pins, see the Virtex-4 RocketIO Multi-Gigabit Transceiver User Guide (UG076).Virtex-4 FPGA Packaging and Pinout Specification www.xilinx.com 17UG075 (v3.3) September 19, 2008

Chapter 1: Packaging OverviewR18 www.xilinx.com Virtex-4 FPGA Packaging and Pinout SpecificationUG075 (v3.3) September 19, 2008

RChapter 2Pinout TablesSummaryThis chapter provides pinout information for the following packages:• SF363 Flip-Chip Fine-Pitch BGA PackageLX15, LX25, and FX12 devices are available in this package.• FF668 Flip-Chip Fine-Pitch BGA PackageLX15, LX25, LX40, LX60, SX25, SX35, and FX12 devices are available in this package.• FF672 Flip-Chip Fine-Pitch BGA PackageFX60, FX40, and FX20 devices are available in this package.• FF676 Flip-Chip Fine-Pitch BGA PackageLX15 and LX25 devices are available in this package.• FF1148 Flip-Chip Fine-Pitch BGA PackageLX40, LX60, LX80, LX100, LX160, and SX55 devices are available in this package.• FF1152 Flip-Chip Fine-Pitch BGA PackageFX100, FX60, and FX40 devices are available in this package.• FF1513 Flip-Chip Fine-Pitch BGA PackageLX100, LX160, and LX200 devices are available in this package.• FF1517 Flip-Chip Fine-Pitch BGA PackageFX140 and FX100 devices are available in this package.Virtex-4 FPGA Packaging and Pinout Specification www.xilinx.com 19UG075 (v3.3) September 19, 2008

Chapter 2: Pinout TablesRSF363 Flip-Chip Fine-Pitch BGA PackageAs shown in Table 2-1, Virtex-4 XC4VLX15, XC4VLX25, and XC4VFX12 devices areavailable in the SF363 flip-chip fine-pitch BGA package. The “No Connect” column inTable 2-1 shows pins that are not available in LX15 devices.To be assured of having the very latest Virtex-4 FPGA pinout information, visitwww.xilinx.com and check for any updates to this document. ASCII package pinout filesare also available for download from the Xilinx website.Table 2-1: SF363 Package — LX15, LX25, and FX12 DevicesBank Pin Description Pin Number0 HSWAPEN_0 E130 CCLK_0 E110 D_IN_0 E90 PROG_B_0 F120 INIT_B_0 E120 CS_B_0 E80 DONE_0 F110 RDWR_B_0 F90 VBATT_0 T130 M2_0 R110 PWRDWN_B_0 T100 TMS_0 T80 M0_0 R120 TDO_0 R100 TCK_0 T90 M1_0 T120 DOUT_BUSY_0 T110 TDI_0 R90 TDN_0 E100 TDP_0 F10No Connectsin LX15 and FX12 Devices1 IO_L1P_D31_LC_1 F151 IO_L1N_D30_LC_1 E151 IO_L2P_D29_LC_1 E61 IO_L2N_D28_LC_1 F61 IO_L3P_D27_LC_1 D151 IO_L3N_D26_LC_1 E141 IO_L4P_D25_LC_1 E71 IO_L4N_D24_VREF_LC_1 D620 www.xilinx.com Virtex-4 FPGA Packaging and Pinout SpecificationUG075 (v3.3) September 19, 2008

RSF363 Flip-Chip Fine-Pitch BGA PackageTable 2-1: SF363 Package — LX15, LX25, and FX12 Devices (Continued)Bank Pin Description Pin Number1 IO_L5P_D23_LC_1 D131 IO_L5N_D22_LC_1 C131 IO_L6P_D21_LC_1 C81 IO_L6N_D20_LC_1 D81 IO_L7P_D19_LC_1 D121 IO_L7N_D18_LC_1 C121 IO_L8P_D17_CC_LC_1 C91 IO_L8N_D16_CC_LC_1 D9No Connectsin LX15 and FX12 Devices2 IO_L1P_D15_CC_LC_2 V162 IO_L1N_D14_CC_LC_2 V152 IO_L2P_D13_LC_2 V62 IO_L2N_D12_LC_2 V52 IO_L3P_D11_LC_2 T142 IO_L3N_D10_LC_2 U132 IO_L4P_D9_LC_2 U82 IO_L4N_D8_VREF_LC_2 T72 IO_L5P_D7_LC_2 V132 IO_L5N_D6_LC_2 V122 IO_L6P_D5_LC_2 V92 IO_L6N_D4_LC_2 V82 IO_L7P_D3_LC_2 U122 IO_L7N_D2_LC_2 V112 IO_L8P_D1_LC_2 V102 IO_L8N_D0_LC_2 U93 IO_L1P_GC_CC_LC_3 B123 IO_L1N_GC_CC_LC_3 A113 IO_L2P_GC_VRN_LC_3 A103 IO_L2N_GC_VRP_LC_3 B93 IO_L3P_GC_LC_3 C113 IO_L3N_GC_LC_3 B113 IO_L4P_GC_LC_3 B103 IO_L4N_GC_VREF_LC_3 C103 IO_L5P_GC_LC_3 B13Virtex-4 FPGA Packaging and Pinout Specification www.xilinx.com 21UG075 (v3.3) September 19, 2008

Chapter 2: Pinout TablesRTable 2-1: SF363 Package — LX15, LX25, and FX12 Devices (Continued)Bank Pin Description Pin Number3 IO_L5N_GC_LC_3 A133 IO_L6P_GC_LC_3 A83 IO_L6N_GC_LC_3 B83 IO_L7P_GC_LC_3 B143 IO_L7N_GC_LC_3 A143 IO_L8P_GC_LC_3 A73 IO_L8N_GC_LC_3 B7No Connectsin LX15 and FX12 Devices4 IO_L1P_GC_LC_4 W134 IO_L1N_GC_LC_4 W124 IO_L2P_GC_LC_4 Y54 IO_L2N_GC_LC_4 W54 IO_L3P_GC_LC_4 Y124 IO_L3N_GC_LC_4 Y114 IO_L4P_GC_LC_4 Y64 IO_L4N_GC_VREF_LC_4 W64 IO_L5P_GC_LC_4 W114 IO_L5N_GC_LC_4 W104 IO_L6P_GC_LC_4 Y74 IO_L6N_GC_LC_4 W74 IO_L7P_GC_VRN_LC_4 Y104 IO_L7N_GC_VRP_LC_4 Y94 IO_L8P_GC_CC_LC_4 W94 IO_L8N_GC_CC_LC_4 W85 IO_L1P_5 B155 IO_L1N_5 A155 IO_L2P_5 A165 IO_L2N_5 B165 IO_L3P_5 C155 IO_L3N_5 C165 IO_L4P_5 B175 IO_L4N_VREF_5 C175 IO_L5P_5 D165 IO_L5N_5 E1622 www.xilinx.com Virtex-4 FPGA Packaging and Pinout SpecificationUG075 (v3.3) September 19, 2008

RSF363 Flip-Chip Fine-Pitch BGA PackageTable 2-1: SF363 Package — LX15, LX25, and FX12 Devices (Continued)Bank Pin Description Pin Number5 IO_L6P_5 A185 IO_L6N_5 B185 IO_L7P_5 D175 IO_L7N_5 D185 IO_L8P_CC_LC_5 B195 IO_L8N_CC_LC_5 C205 IO_L17P_5 J175 IO_L17N_5 J185 IO_L18P_5 H205 IO_L18N_5 G205 IO_L19P_5 J155 IO_L19N_5 J165 IO_L20P_5 H185 IO_L20N_VREF_5 H195 IO_L21P_5 K165 IO_L21N_5 K175 IO_L22P_5 K205 IO_L22N_5 J195 IO_L23P_VRN_5 L165 IO_L23N_VRP_5 L175 IO_L24P_CC_LC_5 K185 IO_L24N_CC_LC_5 K195 IO_L9P_CC_LC_5 F185 IO_L9N_CC_LC_5 E185 IO_L10P_5 C185 IO_L10N_5 C195 IO_L11P_5 F165 IO_L11N_5 F175 IO_L12P_5 D195 IO_L12N_VREF_5 E195 IO_L13P_5 G165 IO_L13N_5 G175 IO_L14P_5 E205 IO_L14N_5 F205 IO_L15P_5 H165 IO_L15N_5 H17No Connectsin LX15 and FX12 DevicesVirtex-4 FPGA Packaging and Pinout Specification www.xilinx.com 23UG075 (v3.3) September 19, 2008

Chapter 2: Pinout TablesRTable 2-1: SF363 Package — LX15, LX25, and FX12 Devices (Continued)Bank Pin Description Pin Number5 IO_L16P_5 F195 IO_L16N_5 G195 IO_L25P_CC_LC_5 M175 IO_L25N_CC_LC_5 M185 IO_L26P_5 M205 IO_L26N_5 L205 IO_L27P_5 M155 IO_L27N_5 M165 IO_L28P_5 M195 IO_L28N_VREF_5 L195 IO_L29P_5 N165 IO_L29N_5 N175 IO_L30P_5 N185 IO_L30N_5 N195 IO_L31P_5 P165 IO_L31N_5 P175 IO_L32P_5 P195 IO_L32N_5 P20No Connectsin LX15 and FX12 Devices6 IO_L1P_6 B66 IO_L1N_6 A66 IO_L2P_6 A56 IO_L2N_6 B56 IO_L3P_6 C66 IO_L3N_6 C56 IO_L4P_6 B46 IO_L4N_VREF_6 C46 IO_L5P_6 D56 IO_L5N_6 E56 IO_L6P_6 A36 IO_L6N_6 B36 IO_L7P_6 D46 IO_L7N_6 D36 IO_L8P_CC_LC_6 B26 IO_L8N_CC_LC_6 C124 www.xilinx.com Virtex-4 FPGA Packaging and Pinout SpecificationUG075 (v3.3) September 19, 2008

RSF363 Flip-Chip Fine-Pitch BGA PackageTable 2-1: SF363 Package — LX15, LX25, and FX12 Devices (Continued)Bank Pin Description Pin Number6 IO_L17P_6 J46 IO_L17N_6 J36 IO_L18P_6 H16 IO_L18N_6 G16 IO_L19P_6 J66 IO_L19N_6 J56 IO_L20P_6 H36 IO_L20N_VREF_6 H26 IO_L21P_6 K56 IO_L21N_6 K46 IO_L22P_6 K16 IO_L22N_6 J26 IO_L23P_VRN_6 L56 IO_L23N_VRP_6 L46 IO_L24P_CC_LC_6 K36 IO_L24N_CC_LC_6 K26 IO_L9P_CC_LC_6 F36 IO_L9N_CC_LC_6 E36 IO_L10P_6 C36 IO_L10N_6 C26 IO_L11P_6 F56 IO_L11N_6 F46 IO_L12P_6 D26 IO_L12N_VREF_6 E26 IO_L13P_6 G56 IO_L13N_6 G46 IO_L14P_6 E16 IO_L14N_6 F16 IO_L15P_6 H56 IO_L15N_6 H46 IO_L16P_6 F26 IO_L16N_6 G26 IO_L25P_CC_LC_6 M46 IO_L25N_CC_LC_6 M36 IO_L26P_6 M16 IO_L26N_6 L1No Connectsin LX15 and FX12 DevicesVirtex-4 FPGA Packaging and Pinout Specification www.xilinx.com 25UG075 (v3.3) September 19, 2008

Chapter 2: Pinout TablesRTable 2-1: SF363 Package — LX15, LX25, and FX12 Devices (Continued)Bank Pin Description Pin Number6 IO_L27P_6 M66 IO_L27N_6 M56 IO_L28P_6 M26 IO_L28N_VREF_6 L26 IO_L29P_6 N56 IO_L29N_6 N46 IO_L30P_6 N36 IO_L30N_6 N26 IO_L31P_6 P56 IO_L31N_6 P46 IO_L32P_6 P26 IO_L32N_6 P1No Connectsin LX15 and FX12 Devices7 IO_L25P_CC_SM7_LC_7 T177 IO_L25N_CC_SM7_LC_7 T187 IO_L26P_SM6_7 U187 IO_L26N_SM6_7 U197 IO_L27P_SM5_7 T157 IO_L27N_SM5_7 U157 IO_L28P_7 V197 IO_L28N_VREF_7 V207 IO_L29P_SM4_7 U167 IO_L29N_SM4_7 U177 IO_L30P_SM3_7 W187 IO_L30N_SM3_7 W197 IO_L31P_SM2_7 Y177 IO_L31N_SM2_7 W177 IO_L32P_SM1_7 V177 IO_L32N_SM1_7 V187 IO_L20P_7 R197 IO_L20N_VREF_7 R207 IO_L21P_7 R157 IO_L21N_7 R167 IO_L23P_VRN_7 T197 IO_L23N_VRP_7 T2026 www.xilinx.com Virtex-4 FPGA Packaging and Pinout SpecificationUG075 (v3.3) September 19, 2008

RSF363 Flip-Chip Fine-Pitch BGA PackageTable 2-1: SF363 Package — LX15, LX25, and FX12 Devices (Continued)Bank Pin Description Pin Number7 IO_L24P_CC_LC_7 R177 IO_L24N_CC_LC_7 R18No Connectsin LX15 and FX12 Devices8 IO_L25P_CC_LC_8 U38 IO_L25N_CC_LC_8 U28 IO_L26P_8 T48 IO_L26N_8 T38 IO_L27P_8 T68 IO_L27N_8 U68 IO_L28P_8 V28 IO_L28N_VREF_8 V18 IO_L29P_8 U58 IO_L29N_8 U48 IO_L30P_8 W38 IO_L30N_8 W28 IO_L31P_8 Y48 IO_L31N_8 W48 IO_L32P_8 V48 IO_L32N_8 V38 IO_L20P_8 R28 IO_L20N_VREF_8 R18 IO_L21P_8 R68 IO_L21N_8 R58 IO_L23P_VRN_8 T28 IO_L23N_VRP_8 T18 IO_L24P_CC_LC_8 R48 IO_L24N_CC_LC_8 R30 VCCO_0 (1) D100 VCCO_0 (1) U111 VCCO_1 D71 VCCO_1 D142 VCCO_2 U72 VCCO_2 U143 VCCO_3 A9Virtex-4 FPGA Packaging and Pinout Specification www.xilinx.com 27UG075 (v3.3) September 19, 2008

Chapter 2: Pinout TablesRTable 2-1: SF363 Package — LX15, LX25, and FX12 Devices (Continued)Bank Pin Description Pin Number3 VCCO_3 A124 VCCO_4 Y84 VCCO_4 Y135 VCCO_5 K155 VCCO_5 L155 VCCO_5 A175 VCCO_5 E175 VCCO_5 L185 VCCO_5 D205 VCCO_5 J205 VCCO_5 N206 VCCO_6 D16 VCCO_6 J16 VCCO_6 N16 VCCO_6 L36 VCCO_6 A46 VCCO_6 E46 VCCO_6 K66 VCCO_6 L67 VCCO_7 T167 VCCO_7 Y187 VCCO_7 U208 VCCO_8 U18 VCCO_8 Y38 VCCO_8 T5No Connectsin LX15 and FX12 DevicesN/A VREFP_SM (2) W14 NCN/A VREFN_SM (2) W15 NCN/A AVDD_SM (3) W16 NCN/A VP_SM (2) Y14 NCN/A VN_SM (2) Y15 NCN/A AVSS_SM (2) Y16 NCN/A GND B1N/A GND W128 www.xilinx.com Virtex-4 FPGA Packaging and Pinout SpecificationUG075 (v3.3) September 19, 2008

RSF363 Flip-Chip Fine-Pitch BGA PackageTable 2-1: SF363 Package — LX15, LX25, and FX12 Devices (Continued)Bank Pin Description Pin NumberN/A GND Y1N/A GND A2N/A GND Y2N/A GND G3N/A GND P3N/A GND C7N/A GND H7N/A GND J7N/A GND K7N/A GND L7N/A GND M7N/A GND N7N/A GND V7N/A GND G8N/A GND P8N/A GND G9N/A GND P9N/A GND G10N/A GND P10N/A GND U10N/A GND D11N/A GND G11N/A GND P11N/A GND G12N/A GND P12N/A GND G13N/A GND P13N/A GND C14N/A GND H14N/A GND J14N/A GND K14N/A GND L14N/A GND M14N/A GND N14N/A GND V14N/A GND G18No Connectsin LX15 and FX12 DevicesVirtex-4 FPGA Packaging and Pinout Specification www.xilinx.com 29UG075 (v3.3) September 19, 2008

Chapter 2: Pinout TablesRTable 2-1: SF363 Package — LX15, LX25, and FX12 Devices (Continued)Bank Pin Description Pin NumberNo Connectsin LX15 and FX12 DevicesN/A GND P18N/A GND A19N/A GND Y19N/A GND A20N/A GND B20N/A GND W20N/A GND Y20N/A VCCAUX H6N/A VCCAUX N6N/A VCCAUX F8N/A VCCAUX R8N/A VCCAUX F13N/A VCCAUX R13N/A VCCAUX H15N/A VCCAUX N15N/A VCCINT G6N/A VCCINT P6N/A VCCINT F7N/A VCCINT G7N/A VCCINT P7N/A VCCINT R7N/A VCCINT F14N/A VCCINT G14N/A VCCINT P14N/A VCCINT R14N/A VCCINT G15N/A VCCINT P15Notes:1. This voltage is also referred to as V CC_CONFIG in the Virtex-4 Configuration Guide.2. Connect this reserved pin to GND.3. Connect this reserved pin to 2.5V (sharing the same PCB supply distribution as V CCAUX is acceptable).30 www.xilinx.com Virtex-4 FPGA Packaging and Pinout SpecificationUG075 (v3.3) September 19, 2008

RFF668 Flip-Chip Fine-Pitch BGA PackageFF668 Flip-Chip Fine-Pitch BGA PackageAs shown in Table 2-2, the following Virtex-4 LX and SX devices are available in the FF668flip-chip fine-pitch BGA package:• XC4VLX15• XC4VLX25• XC4VLX40• XC4VLX60• XC4VSX25• XC4VSX35• XC4VFX12Pinouts in the following devices are identical:• LX15, SX25, and FX12• LX25, LX40, LX60, and SX35The “No Connect” column in Table 2-2 shows pins that are not available in LX15, SX25,and FX12 devices.To be assured of having the very latest Virtex-4 FPGA pinout information, visitwww.xilinx.com and check for any updates to this document. ASCII package pinout filesare also available for download from the Xilinx website.Table 2-2: FF668 Package — LX15, LX25, LX40, LX60, SX25, SX35, and FX12DevicesBank Pin Description Pin Number0 HSWAPEN_0 G160 CCLK_0 G140 D_IN_0 G120 PROG_B_0 H150 INIT_B_0 G150 CS_B_0 G110 DONE_0 H140 RDWR_B_0 H120 VBATT_0 Y160 M2_0 W140 PWRDWN_B_0 W130 TMS_0 Y110 M0_0 W150 TDO_0 Y130 TCK_0 W12No Connects inLX15, SX25, and FX12 DevicesVirtex-4 FPGA Packaging and Pinout Specification www.xilinx.com 31UG075 (v3.3) September 19, 2008

Chapter 2: Pinout TablesRTable 2-2: FF668 Package — LX15, LX25, LX40, LX60, SX25, SX35, and FX12Devices (Continued)Bank Pin Description Pin Number0 M1_0 Y150 DOUT_BUSY_0 Y140 TDI_0 Y120 TDN_0 G130 TDP_0 H13No Connects inLX15, SX25, and FX12 Devices1 IO_L1P_D31_LC_1 F141 IO_L1N_D30_LC_1 F131 IO_L2P_D29_LC_1 F121 IO_L2N_D28_LC_1 F111 IO_L3P_D27_LC_1 F161 IO_L3N_D26_LC_1 F151 IO_L4P_D25_LC_1 D141 IO_L4N_D24_VREF_LC_1 D131 IO_L5P_D23_LC_1 D151 IO_L5N_D22_LC_1 E141 IO_L6P_D21_LC_1 C111 IO_L6N_D20_LC_1 D111 IO_L7P_D19_LC_1 D161 IO_L7N_D18_LC_1 C161 IO_L8P_D17_CC_LC_1 E131 IO_L8N_D16_CC_LC_1 D122 IO_L1P_D15_CC_LC_2 AA142 IO_L1N_D14_CC_LC_2 AB142 IO_L2P_D13_LC_2 AC122 IO_L2N_D12_LC_2 AC112 IO_L3P_D11_LC_2 AA162 IO_L3N_D10_LC_2 AA152 IO_L4P_D9_LC_2 AB132 IO_L4N_D8_VREF_LC_2 AA132 IO_L5P_D7_LC_2 AC142 IO_L5N_D6_LC_2 AD142 IO_L6P_D5_LC_2 AA122 IO_L6N_D4_LC_2 AA112 IO_L7P_D3_LC_2 AC1632 www.xilinx.com Virtex-4 FPGA Packaging and Pinout SpecificationUG075 (v3.3) September 19, 2008

RFF668 Flip-Chip Fine-Pitch BGA PackageTable 2-2: FF668 Package — LX15, LX25, LX40, LX60, SX25, SX35, and FX12Devices (Continued)Bank Pin Description Pin Number2 IO_L7N_D2_LC_2 AC152 IO_L8P_D1_LC_2 AC132 IO_L8N_D0_LC_2 AD13No Connects inLX15, SX25, and FX12 Devices3 IO_L1P_GC_CC_LC_3 B153 IO_L1N_GC_CC_LC_3 B143 IO_L2P_GC_VRN_LC_3 A123 IO_L2N_GC_VRP_LC_3 A113 IO_L3P_GC_LC_3 C153 IO_L3N_GC_LC_3 C143 IO_L4P_GC_LC_3 B133 IO_L4N_GC_VREF_LC_3 B123 IO_L5P_GC_LC_3 A163 IO_L5N_GC_LC_3 A153 IO_L6P_GC_LC_3 A103 IO_L6N_GC_LC_3 B103 IO_L7P_GC_LC_3 B173 IO_L7N_GC_LC_3 A173 IO_L8P_GC_LC_3 C133 IO_L8N_GC_LC_3 C124 IO_L1P_GC_LC_4 AF124 IO_L1N_GC_LC_4 AE124 IO_L2P_GC_LC_4 AC104 IO_L2N_GC_LC_4 AB104 IO_L3P_GC_LC_4 AB174 IO_L3N_GC_LC_4 AC174 IO_L4P_GC_LC_4 AF114 IO_L4N_GC_VREF_LC_4 AF104 IO_L5P_GC_LC_4 AE144 IO_L5N_GC_LC_4 AE134 IO_L6P_GC_LC_4 AE104 IO_L6N_GC_LC_4 AD104 IO_L7P_GC_VRN_LC_4 AD174 IO_L7N_GC_VRP_LC_4 AD164 IO_L8P_GC_CC_LC_4 AD12Virtex-4 FPGA Packaging and Pinout Specification www.xilinx.com 33UG075 (v3.3) September 19, 2008

Chapter 2: Pinout TablesRTable 2-2: FF668 Package — LX15, LX25, LX40, LX60, SX25, SX35, and FX12Devices (Continued)Bank Pin Description Pin Number4 IO_L8N_GC_CC_LC_4 AD11No Connects inLX15, SX25, and FX12 Devices5 IO_L1P_5 C175 IO_L1N_5 D175 IO_L2P_5 C205 IO_L2N_5 B205 IO_L3P_5 B185 IO_L3N_5 A185 IO_L4P_5 D205 IO_L4N_VREF_5 D195 IO_L5P_5 E175 IO_L5N_5 F175 IO_L6P_5 C215 IO_L6N_5 B215 IO_L7P_5 C195 IO_L7N_5 D185 IO_L8P_CC_LC_5 A245 IO_L8N_CC_LC_5 A235 IO_L17P_5 G195 IO_L17N_5 F195 IO_L18P_5 E235 IO_L18N_5 E225 IO_L19P_5 F205 IO_L19N_5 E205 IO_L20P_5 C265 IO_L20N_VREF_5 C255 IO_L21P_5 D235 IO_L21N_5 C235 IO_L22P_5 H205 IO_L22N_5 G205 IO_L23P_VRN_5 G225 IO_L23N_VRP_5 G215 IO_L24P_CC_LC_5 F245 IO_L24N_CC_LC_5 F235 IO_L9P_CC_LC_5 G185 IO_L9N_CC_LC_5 G1734 www.xilinx.com Virtex-4 FPGA Packaging and Pinout SpecificationUG075 (v3.3) September 19, 2008

RFF668 Flip-Chip Fine-Pitch BGA PackageTable 2-2: FF668 Package — LX15, LX25, LX40, LX60, SX25, SX35, and FX12Devices (Continued)Bank Pin Description Pin Number5 IO_L10P_5 B245 IO_L10N_5 B235 IO_L11P_5 F185 IO_L11N_5 E185 IO_L12P_5 E215 IO_L12N_VREF_5 D215 IO_L13P_5 A205 IO_L13N_5 A195 IO_L14P_5 D225 IO_L14N_5 C225 IO_L15P_5 A225 IO_L15N_5 A215 IO_L16P_5 D245 IO_L16N_5 C245 IO_L25P_CC_LC_5 D265 IO_L25N_CC_LC_5 D255 IO_L26P_5 H225 IO_L26N_5 H215 IO_L27P_5 E255 IO_L27N_5 E245 IO_L28P_5 G245 IO_L28N_VREF_5 G235 IO_L29P_5 F265 IO_L29N_5 E265 IO_L30P_5 H245 IO_L30N_5 H235 IO_L31P_5 G265 IO_L31N_5 G255 IO_L32P_5 H265 IO_L32N_5 H25No Connects inLX15, SX25, and FX12 Devices6 IO_L1P_6 D106 IO_L1N_6 C106 IO_L2P_6 D96 IO_L2N_6 C86 IO_L3P_6 A8Virtex-4 FPGA Packaging and Pinout Specification www.xilinx.com 35UG075 (v3.3) September 19, 2008

Chapter 2: Pinout TablesRTable 2-2: FF668 Package — LX15, LX25, LX40, LX60, SX25, SX35, and FX12Devices (Continued)Bank Pin Description Pin Number6 IO_L3N_6 A76 IO_L4P_6 D86 IO_L4N_VREF_6 D76 IO_L5P_6 F106 IO_L5N_6 E106 IO_L6P_6 A66 IO_L6N_6 A56 IO_L7P_6 E96 IO_L7N_6 F96 IO_L8P_CC_LC_6 B66 IO_L8N_CC_LC_6 C66 IO_L17P_6 E76 IO_L17N_6 D66 IO_L18P_6 E66 IO_L18N_6 E56 IO_L19P_6 F76 IO_L19N_6 G76 IO_L20P_6 C26 IO_L20N_VREF_6 C16 IO_L21P_6 H86 IO_L21N_6 H76 IO_L22P_6 D36 IO_L22N_6 E46 IO_L23P_VRN_6 G66 IO_L23N_VRP_6 G56 IO_L24P_CC_LC_6 E36 IO_L24N_CC_LC_6 E26 IO_L9P_CC_LC_6 G106 IO_L9N_CC_LC_6 G96 IO_L10P_6 F86 IO_L10N_6 G86 IO_L11P_6 B76 IO_L11N_6 C76 IO_L12P_6 C56 IO_L12N_VREF_6 D56 IO_L13P_6 A9No Connects inLX15, SX25, and FX12 Devices36 www.xilinx.com Virtex-4 FPGA Packaging and Pinout SpecificationUG075 (v3.3) September 19, 2008

RFF668 Flip-Chip Fine-Pitch BGA PackageTable 2-2: FF668 Package — LX15, LX25, LX40, LX60, SX25, SX35, and FX12Devices (Continued)Bank Pin Description Pin Number6 IO_L13N_6 B96 IO_L14P_6 A36 IO_L14N_6 B36 IO_L15P_6 A46 IO_L15N_6 B46 IO_L16P_6 C46 IO_L16N_6 D46 IO_L25P_CC_LC_6 D26 IO_L25N_CC_LC_6 D16 IO_L26P_6 E16 IO_L26N_6 F16 IO_L27P_6 F46 IO_L27N_6 F36 IO_L28P_6 G46 IO_L28N_VREF_6 G36 IO_L29P_6 H66 IO_L29N_6 H56 IO_L30P_6 G26 IO_L30N_6 G16 IO_L31P_6 H46 IO_L31N_6 H36 IO_L32P_6 H26 IO_L32N_6 H1No Connects inLX15, SX25, and FX12 Devices7 IO_L25P_CC_SM7_LC_7 AD197 IO_L25N_CC_SM7_LC_7 AC197 IO_L26P_SM6_7 AA197 IO_L26N_SM6_7 AA207 IO_L27P_SM5_7 Y177 IO_L27N_SM5_7 AA177 IO_L28P_7 AB207 IO_L28N_VREF_7 AC207 IO_L29P_SM4_7 AC187 IO_L29N_SM4_7 AB187 IO_L30P_SM3_7 AF217 IO_L30N_SM3_7 AF22Virtex-4 FPGA Packaging and Pinout Specification www.xilinx.com 37UG075 (v3.3) September 19, 2008

Chapter 2: Pinout TablesRTable 2-2: FF668 Package — LX15, LX25, LX40, LX60, SX25, SX35, and FX12Devices (Continued)Bank Pin Description Pin Number7 IO_L31P_SM2_7 AF187 IO_L31N_SM2_7 AE187 IO_L32P_SM1_7 AE217 IO_L32N_SM1_7 AD217 IO_L17P_7 AF197 IO_L17N_7 AF207 IO_L18P_7 Y197 IO_L18N_7 W197 IO_L19P_7 AF237 IO_L19N_7 AE237 IO_L20P_7 Y207 IO_L20N_VREF_7 Y217 IO_L21P_7 AA187 IO_L21N_7 Y187 IO_L22P_7 AF247 IO_L22N_7 AE247 IO_L23P_VRN_7 AE207 IO_L23N_VRP_7 AD207 IO_L24P_CC_LC_7 AC217 IO_L24N_CC_LC_7 AB217 IO_L1P_7 V217 IO_L1N_7 V227 IO_L2P_7 W257 IO_L2N_7 W267 IO_L3P_7 W217 IO_L3N_7 W227 IO_L4P_7 W237 IO_L4N_VREF_7 W247 IO_L5P_7 W207 IO_L5N_7 V207 IO_L6P_7 Y257 IO_L6N_7 Y267 IO_L7P_7 AB247 IO_L7N_7 AB257 IO_L8P_CC_LC_7 AA247 IO_L8N_CC_LC_7 Y24No Connects inLX15, SX25, and FX12 Devices38 www.xilinx.com Virtex-4 FPGA Packaging and Pinout SpecificationUG075 (v3.3) September 19, 2008

RFF668 Flip-Chip Fine-Pitch BGA PackageTable 2-2: FF668 Package — LX15, LX25, LX40, LX60, SX25, SX35, and FX12Devices (Continued)Bank Pin Description Pin Number7 IO_L9P_CC_LC_7 AC257 IO_L9N_CC_LC_7 AC267 IO_L10P_7 AB267 IO_L10N_7 AA267 IO_L11P_7 AD257 IO_L11N_7 AD267 IO_L12P_7 Y227 IO_L12N_VREF_7 Y237 IO_L13P_7 AC227 IO_L13N_7 AB227 IO_L14P_7 AB237 IO_L14N_7 AA237 IO_L15P_7 AD227 IO_L15N_7 AD237 IO_L16P_7 AC237 IO_L16N_7 AC24No Connects inLX15, SX25, and FX12 Devices8 IO_L25P_CC_LC_8 AF88 IO_L25N_CC_LC_8 AF78 IO_L26P_8 AA88 IO_L26N_8 Y88 IO_L27P_8 Y108 IO_L27N_8 AA108 IO_L28P_8 AC78 IO_L28N_VREF_8 AB78 IO_L29P_8 AC98 IO_L29N_8 AB98 IO_L30P_8 AE68 IO_L30N_8 AD68 IO_L31P_8 AF98 IO_L31N_8 AE98 IO_L32P_8 AD88 IO_L32N_8 AC88 IO_L17P_8 AF48 IO_L17N_8 AE48 IO_L18P_8 AD3Virtex-4 FPGA Packaging and Pinout Specification www.xilinx.com 39UG075 (v3.3) September 19, 2008

Chapter 2: Pinout TablesRTable 2-2: FF668 Package — LX15, LX25, LX40, LX60, SX25, SX35, and FX12Devices (Continued)Bank Pin Description Pin Number8 IO_L18N_8 AC38 IO_L19P_8 AF68 IO_L19N_8 AF58 IO_L20P_8 AA78 IO_L20N_VREF_8 Y78 IO_L21P_8 AA98 IO_L21N_8 Y98 IO_L22P_8 AD58 IO_L22N_8 AD48 IO_L23P_VRN_8 AE78 IO_L23N_VRP_8 AD78 IO_L24P_CC_LC_8 AC68 IO_L24N_CC_LC_8 AB68 IO_L1P_8 W28 IO_L1N_8 W18 IO_L2P_8 V68 IO_L2N_8 V58 IO_L3P_8 W78 IO_L3N_8 V78 IO_L4P_8 W48 IO_L4N_VREF_8 W38 IO_L5P_8 W68 IO_L5N_8 W58 IO_L6P_8 Y28 IO_L6N_8 Y18 IO_L7P_8 AA48 IO_L7N_8 AA38 IO_L8P_CC_LC_8 Y48 IO_L8N_CC_LC_8 Y38 IO_L9P_CC_LC_8 Y68 IO_L9N_CC_LC_8 Y58 IO_L10P_8 AB18 IO_L10N_8 AA18 IO_L11P_8 AC48 IO_L11N_8 AB48 IO_L12P_8 AB3No Connects inLX15, SX25, and FX12 Devices40 www.xilinx.com Virtex-4 FPGA Packaging and Pinout SpecificationUG075 (v3.3) September 19, 2008

RFF668 Flip-Chip Fine-Pitch BGA PackageTable 2-2: FF668 Package — LX15, LX25, LX40, LX60, SX25, SX35, and FX12Devices (Continued)Bank Pin Description Pin Number8 IO_L12N_VREF_8 AB28 IO_L13P_8 AC58 IO_L13N_8 AB58 IO_L14P_8 AC28 IO_L14N_8 AC18 IO_L15P_8 AF38 IO_L15N_8 AE38 IO_L16P_8 AD28 IO_L16N_8 AD1No Connects inLX15, SX25, and FX12 Devices9 IO_L17P_9 N21 NC9 IO_L17N_9 N20 NC9 IO_L18P_9 P25 NC9 IO_L18N_9 P24 NC9 IO_L19P_9 P23 NC9 IO_L19N_9 P22 NC9 IO_L20P_9 R26 NC9 IO_L20N_VREF_9 R25 NC9 IO_L21P_9 P20 NC9 IO_L21N_9 P19 NC9 IO_L22P_9 R24 NC9 IO_L22N_9 R23 NC9 IO_L23P_VRN_9 R22 NC9 IO_L23N_VRP_9 R21 NC9 IO_L24P_CC_LC_9 T24 NC9 IO_L24N_CC_LC_9 T23 NC9 IO_L1P_9 J21 NC9 IO_L1N_9 J20 NC9 IO_L2P_9 J23 NC9 IO_L2N_9 J22 NC9 IO_L3P_9 K22 NC9 IO_L3N_9 K21 NC9 IO_L4P_9 J26 NC9 IO_L4N_VREF_9 J25 NC9 IO_L5P_9 L19 NC9 IO_L5N_9 K20 NCVirtex-4 FPGA Packaging and Pinout Specification www.xilinx.com 41UG075 (v3.3) September 19, 2008

Chapter 2: Pinout TablesRTable 2-2: FF668 Package — LX15, LX25, LX40, LX60, SX25, SX35, and FX12Devices (Continued)Bank Pin Description Pin NumberNo Connects inLX15, SX25, and FX12 Devices9 IO_L6P_9 L21 NC9 IO_L6N_9 L20 NC9 IO_L7P_9 K24 NC9 IO_L7N_9 K23 NC9 IO_L8P_CC_LC_9 K26 NC9 IO_L8N_CC_LC_9 K25 NC9 IO_L9P_CC_LC_9 M19 NC9 IO_L9N_CC_LC_9 N19 NC9 IO_L10P_9 L24 NC9 IO_L10N_9 L23 NC9 IO_L11P_9 M25 NC9 IO_L11N_9 M24 NC9 IO_L12P_9 L26 NC9 IO_L12N_VREF_9 M26 NC9 IO_L13P_9 M21 NC9 IO_L13N_9 M20 NC9 IO_L14P_9 M23 NC9 IO_L14N_9 M22 NC9 IO_L15P_9 N25 NC9 IO_L15N_9 N24 NC9 IO_L16P_9 N23 NC9 IO_L16N_9 N22 NC9 IO_L25P_CC_LC_9 R20 NC9 IO_L25N_CC_LC_9 R19 NC9 IO_L26P_9 T26 NC9 IO_L26N_9 U26 NC9 IO_L27P_9 U23 NC9 IO_L27N_9 V23 NC9 IO_L28P_9 U25 NC9 IO_L28N_VREF_9 U24 NC9 IO_L29P_9 U22 NC9 IO_L29N_9 U21 NC9 IO_L30P_9 T21 NC9 IO_L30N_9 T20 NC9 IO_L31P_9 U20 NC9 IO_L31N_9 T19 NC42 www.xilinx.com Virtex-4 FPGA Packaging and Pinout SpecificationUG075 (v3.3) September 19, 2008

RFF668 Flip-Chip Fine-Pitch BGA PackageTable 2-2: FF668 Package — LX15, LX25, LX40, LX60, SX25, SX35, and FX12Devices (Continued)Bank Pin Description Pin NumberNo Connects inLX15, SX25, and FX12 Devices9 IO_L32P_9 V26 NC9 IO_L32N_9 V25 NC10 IO_L17P_10 N7 NC10 IO_L17N_10 M7 NC10 IO_L18P_10 P5 NC10 IO_L18N_10 P4 NC10 IO_L19P_10 P8 NC10 IO_L19N_10 N8 NC10 IO_L20P_10 R4 NC10 IO_L20N_VREF_10 R3 NC10 IO_L21P_10 P7 NC10 IO_L21N_10 P6 NC10 IO_L22P_10 R2 NC10 IO_L22N_10 R1 NC10 IO_L23P_VRN_10 R6 NC10 IO_L23N_VRP_10 R5 NC10 IO_L24P_CC_LC_10 U1 NC10 IO_L24N_CC_LC_10 T1 NC10 IO_L1P_10 J7 NC10 IO_L1N_10 J6 NC10 IO_L2P_10 J5 NC10 IO_L2N_10 J4 NC10 IO_L3P_10 K7 NC10 IO_L3N_10 K6 NC10 IO_L4P_10 J2 NC10 IO_L4N_VREF_10 J1 NC10 IO_L5P_10 L7 NC10 IO_L5N_10 L6 NC10 IO_L6P_10 K5 NC10 IO_L6N_10 K4 NC10 IO_L7P_10 K3 NC10 IO_L7N_10 K2 NC10 IO_L8P_CC_LC_10 L4 NC10 IO_L8N_CC_LC_10 L3 NC10 IO_L9P_CC_LC_10 M8 NCVirtex-4 FPGA Packaging and Pinout Specification www.xilinx.com 43UG075 (v3.3) September 19, 2008

Chapter 2: Pinout TablesRTable 2-2: FF668 Package — LX15, LX25, LX40, LX60, SX25, SX35, and FX12Devices (Continued)Bank Pin Description Pin NumberNo Connects inLX15, SX25, and FX12 Devices10 IO_L9N_CC_LC_10 L8 NC10 IO_L10P_10 L1 NC10 IO_L10N_10 K1 NC10 IO_L11P_10 M2 NC10 IO_L11N_10 M1 NC10 IO_L12P_10 M4 NC10 IO_L12N_VREF_10 M3 NC10 IO_L13P_10 M6 NC10 IO_L13N_10 M5 NC10 IO_L14P_10 N3 NC10 IO_L14N_10 N2 NC10 IO_L15P_10 N5 NC10 IO_L15N_10 N4 NC10 IO_L16P_10 P3 NC10 IO_L16N_10 P2 NC10 IO_L25P_CC_LC_10 R8 NC10 IO_L25N_CC_LC_10 R7 NC10 IO_L26P_10 T4 NC10 IO_L26N_10 T3 NC10 IO_L27P_10 T7 NC10 IO_L27N_10 T6 NC10 IO_L28P_10 U3 NC10 IO_L28N_VREF_10 U2 NC10 IO_L29P_10 V4 NC10 IO_L29N_10 U4 NC10 IO_L30P_10 V2 NC10 IO_L30N_10 V1 NC10 IO_L31P_10 T8 NC10 IO_L31N_10 U7 NC10 IO_L32P_10 U6 NC10 IO_L32N_10 U5 NC0 VCCO_0 (1) V120 VCCO_0 (1) J151 VCCO_1 E111 VCCO_1 E1644 www.xilinx.com Virtex-4 FPGA Packaging and Pinout SpecificationUG075 (v3.3) September 19, 2008

RFF668 Flip-Chip Fine-Pitch BGA PackageTable 2-2: FF668 Package — LX15, LX25, LX40, LX60, SX25, SX35, and FX12Devices (Continued)Bank Pin Description Pin Number2 VCCO_2 AB112 VCCO_2 AB163 VCCO_3 B113 VCCO_3 B164 VCCO_4 AE114 VCCO_4 AD155 VCCO_5 H185 VCCO_5 B195 VCCO_5 E195 VCCO_5 H195 VCCO_5 J195 VCCO_5 B225 VCCO_5 F225 VCCO_5 F256 VCCO_6 F26 VCCO_6 B56 VCCO_6 F56 VCCO_6 B86 VCCO_6 E86 VCCO_6 J86 VCCO_6 H96 VCCO_6 H107 VCCO_7 W177 VCCO_7 W187 VCCO_7 V197 VCCO_7 AB197 VCCO_7 AE197 VCCO_7 AA227 VCCO_7 AE227 VCCO_7 AA258 VCCO_8 AA28 VCCO_8 AA58 VCCO_8 AE58 VCCO_8 V88 VCCO_8 W88 VCCO_8 AB8No Connects inLX15, SX25, and FX12 DevicesVirtex-4 FPGA Packaging and Pinout Specification www.xilinx.com 45UG075 (v3.3) September 19, 2008

Chapter 2: Pinout TablesRTable 2-2: FF668 Package — LX15, LX25, LX40, LX60, SX25, SX35, and FX12Devices (Continued)Bank Pin Description Pin NumberNo Connects inLX15, SX25, and FX12 Devices8 VCCO_8 AE88 VCCO_8 W99 VCCO_9 M18 NC9 VCCO_9 K19 NC9 VCCO_9 U19 NC9 VCCO_9 L22 NC9 VCCO_9 T22 NC9 VCCO_9 L25 NC9 VCCO_9 T25 NC9 VCCO_9 P26 NC10 VCCO_10 N1 NC10 VCCO_10 L2 NC10 VCCO_10 T2 NC10 VCCO_10 L5 NC10 VCCO_10 T5 NC10 VCCO_10 K8 NC10 VCCO_10 U8 NC10 VCCO_10 R9 NCN/A VREFN_SM (2) AE15 NCN/A VREFP_SM (2) AE16 NCN/A AVDD_SM (3) AF17 NCN/A VN_SM (2) AF15 NCN/A VP_SM (2) AF16 NCN/A AVSS_SM (2) AE17 NCN/A GND B1N/A GND P1N/A GND AE1N/A GND A2N/A GND B2N/A GND AE2N/A GND AF2N/A GND C3N/A GND J3N/A GND V346 www.xilinx.com Virtex-4 FPGA Packaging and Pinout SpecificationUG075 (v3.3) September 19, 2008

RFF668 Flip-Chip Fine-Pitch BGA PackageTable 2-2: FF668 Package — LX15, LX25, LX40, LX60, SX25, SX35, and FX12Devices (Continued)Bank Pin Description Pin NumberN/A GND F6N/A GND N6N/A GND AA6N/A GND C9N/A GND AD9N/A GND M10N/A GND N10N/A GND P10N/A GND R10N/A GND K11N/A GND M11N/A GND N11N/A GND P11N/A GND R11N/A GND U11N/A GND E12N/A GND K12N/A GND L12N/A GND N12N/A GND P12N/A GND T12N/A GND U12N/A GND AB12N/A GND A13N/A GND J13N/A GND K13N/A GND L13N/A GND M13N/A GND N13N/A GND P13N/A GND R13N/A GND T13N/A GND U13N/A GND V13N/A GND AF13N/A GND A14No Connects inLX15, SX25, and FX12 DevicesVirtex-4 FPGA Packaging and Pinout Specification www.xilinx.com 47UG075 (v3.3) September 19, 2008

Chapter 2: Pinout TablesRTable 2-2: FF668 Package — LX15, LX25, LX40, LX60, SX25, SX35, and FX12Devices (Continued)Bank Pin Description Pin NumberN/A GND J14N/A GND K14N/A GND L14N/A GND M14N/A GND N14N/A GND P14N/A GND R14N/A GND T14N/A GND U14N/A GND V14N/A GND AF14N/A GND E15N/A GND K15N/A GND L15N/A GND N15N/A GND P15N/A GND T15N/A GND U15N/A GND AB15N/A GND K16N/A GND M16N/A GND N16N/A GND P16N/A GND R16N/A GND U16N/A GND M17N/A GND N17N/A GND P17N/A GND R17N/A GND C18N/A GND AD18N/A GND F21N/A GND P21N/A GND AA21N/A GND J24N/A GND V24No Connects inLX15, SX25, and FX12 Devices48 www.xilinx.com Virtex-4 FPGA Packaging and Pinout SpecificationUG075 (v3.3) September 19, 2008

RFF668 Flip-Chip Fine-Pitch BGA PackageTable 2-2: FF668 Package — LX15, LX25, LX40, LX60, SX25, SX35, and FX12Devices (Continued)Bank Pin Description Pin NumberN/A GND AD24N/A GND A25N/A GND B25N/A GND AE25N/A GND AF25N/A GND B26N/A GND N26N/A GND AE26No Connects inLX15, SX25, and FX12 DevicesN/A VCCAUX M9N/A VCCAUX N9N/A VCCAUX P9N/A VCCAUX W10N/A VCCAUX H11N/A VCCAUX W11N/A VCCAUX J12N/A VCCAUX V15N/A VCCAUX H16N/A VCCAUX W16N/A VCCAUX H17N/A VCCAUX N18N/A VCCAUX P18N/A VCCAUX R18N/A VCCINT K9N/A VCCINT L9N/A VCCINT T9N/A VCCINT U9N/A VCCINT J10N/A VCCINT K10N/A VCCINT L10N/A VCCINT T10N/A VCCINT U10N/A VCCINT V10N/A VCCINT J11N/A VCCINT L11N/A VCCINT T11Virtex-4 FPGA Packaging and Pinout Specification www.xilinx.com 49UG075 (v3.3) September 19, 2008

Chapter 2: Pinout TablesRTable 2-2: FF668 Package — LX15, LX25, LX40, LX60, SX25, SX35, and FX12Devices (Continued)Bank Pin Description Pin NumberNo Connects inLX15, SX25, and FX12 DevicesN/A VCCINT V11N/A VCCINT M12N/A VCCINT R12N/A VCCINT M15N/A VCCINT R15N/A VCCINT J16N/A VCCINT L16N/A VCCINT T16N/A VCCINT V16N/A VCCINT J17N/A VCCINT K17N/A VCCINT L17N/A VCCINT T17N/A VCCINT U17N/A VCCINT V17N/A VCCINT K18N/A VCCINT L18N/A VCCINT T18N/A VCCINT U18Notes:1. This voltage is also referred to as V CC_CONFIG in the Virtex-4 Configuration Guide.2. Connect this reserved pin to GND.3. Connect this reserved pin to 2.5V (sharing the same PCB supply distribution as V CCAUX is acceptable).50 www.xilinx.com Virtex-4 FPGA Packaging and Pinout SpecificationUG075 (v3.3) September 19, 2008

RFF672 Flip-Chip Fine-Pitch BGA PackageFF672 Flip-Chip Fine-Pitch BGA PackageAs shown in Table 2-3, Virtex-4 XC4VFX60, XC4VFX40, and XC4VFX20 devices areavailable in the FF672 flip-chip fine-pitch BGA package.The “No Connect” column in Table 2-3 shows pins that are not available in FX20 devices.To be assured of having the very latest Virtex-4 FPGA pinout information, visitwww.xilinx.com and check for any updates to this document. ASCII package pinout filesare also available for download from the Xilinx website.Table 2-3: FF672 Package — FX60, FX40, and FX20 DevicesBank Pin Description Pin Number No Connects in FX20 Devices0 HSWAPEN_0 K160 CCLK_0 M140 D_IN_0 L130 PROG_B_0 K170 INIT_B_0 L150 CS_B_0 M120 DONE_0 K150 RDWR_B_0 R110 VBATT_0 L170 M2_0 M160 PWRDWN_B_0 U120 TMS_0 T100 M0_0 P140 TDO_0 R130 TCK_0 U100 M1_0 R150 DOUT_BUSY_0 T140 TDI_0 U110 TDN_0 E120 TDP_0 F121 IO_L1P_D31_LC_1 J151 IO_L1N_D30_LC_1 J141 IO_L2P_D29_LC_1 K131 IO_L2N_D28_LC_1 J131 IO_L3P_D27_LC_1 H141 IO_L3N_D26_LC_1 G141 IO_L4P_D25_LC_1 H131 IO_L4N_D24_VREF_LC_1 H121 IO_L5P_D23_LC_1 J16Virtex-4 FPGA Packaging and Pinout Specification www.xilinx.com 51UG075 (v3.3) September 19, 2008

Chapter 2: Pinout TablesRTable 2-3: FF672 Package — FX60, FX40, and FX20 Devices (Continued)Bank Pin Description Pin Number No Connects in FX20 Devices1 IO_L5N_D22_LC_1 H161 IO_L6P_D21_LC_1 K121 IO_L6N_D20_LC_1 K111 IO_L7P_D19_LC_1 G161 IO_L7N_D18_LC_1 G151 IO_L8P_D17_CC_LC_1 H111 IO_L8N_D16_CC_LC_1 J112 IO_L1P_D15_CC_LC_2 V162 IO_L1N_D14_CC_LC_2 W162 IO_L2P_D13_LC_2 Y122 IO_L2N_D12_LC_2 Y112 IO_L3P_D11_LC_2 U162 IO_L3N_D10_LC_2 U152 IO_L4P_D9_LC_2 W112 IO_L4N_D8_VREF_LC_2 V112 IO_L5P_D7_LC_2 W152 IO_L5N_D6_LC_2 W142 IO_L6P_D5_LC_2 Y132 IO_L6N_D4_LC_2 W132 IO_L7P_D3_LC_2 U142 IO_L7N_D2_LC_2 V142 IO_L8P_D1_LC_2 V132 IO_L8N_D0_LC_2 V123 IO_L1P_GC_CC_LC_3 F153 IO_L1N_GC_CC_LC_3 E153 IO_L2P_GC_VRN_LC_3 F143 IO_L2N_GC_VRP_LC_3 F133 IO_L3P_GC_LC_3 D153 IO_L3N_GC_LC_3 D143 IO_L4P_GC_LC_3 D133 IO_L4N_GC_VREF_LC_3 E133 IO_L5P_GC_LC_3 C143 IO_L5N_GC_LC_3 B143 IO_L6P_GC_LC_3 C133 IO_L6N_GC_LC_3 C1252 www.xilinx.com Virtex-4 FPGA Packaging and Pinout SpecificationUG075 (v3.3) September 19, 2008

RFF672 Flip-Chip Fine-Pitch BGA PackageTable 2-3: FF672 Package — FX60, FX40, and FX20 Devices (Continued)Bank Pin Description Pin Number No Connects in FX20 Devices3 IO_L7P_GC_LC_3 A143 IO_L7N_GC_LC_3 A133 IO_L8P_GC_LC_3 A123 IO_L8N_GC_LC_3 B124 IO_L1P_GC_LC_4 AE154 IO_L1N_GC_LC_4 AF154 IO_L2P_GC_LC_4 AF144 IO_L2N_GC_LC_4 AF134 IO_L3P_GC_LC_4 AD154 IO_L3N_GC_LC_4 AD144 IO_L4P_GC_LC_4 AE134 IO_L4N_GC_VREF_LC_4 AD134 IO_L5P_GC_LC_4 AB144 IO_L5N_GC_LC_4 AC144 IO_L6P_GC_LC_4 AC134 IO_L6N_GC_LC_4 AC124 IO_L7P_GC_VRN_LC_4 AA144 IO_L7N_GC_VRP_LC_4 AA134 IO_L8P_GC_CC_LC_4 AB124 IO_L8N_GC_CC_LC_4 AA125 IO_L1P_ADC7_5 G205 IO_L1N_ADC7_5 F205 IO_L2P_ADC6_5 H195 IO_L2N_ADC6_5 J195 IO_L3P_ADC5_5 E225 IO_L3N_ADC5_5 E215 IO_L4P_5 G195 IO_L4N_VREF_5 H185 IO_L5P_ADC4_5 G215 IO_L5N_ADC4_5 F225 IO_L6P_ADC3_5 F195 IO_L6N_ADC3_5 F185 IO_L7P_ADC2_5 E235 IO_L7N_ADC2_5 D235 IO_L8P_CC_ADC1_LC_5 E20Virtex-4 FPGA Packaging and Pinout Specification www.xilinx.com 53UG075 (v3.3) September 19, 2008

Chapter 2: Pinout TablesRTable 2-3: FF672 Package — FX60, FX40, and FX20 Devices (Continued)Bank Pin Description Pin Number No Connects in FX20 Devices5 IO_L8N_CC_ADC1_LC_5 D205 IO_L17P_5 K205 IO_L17N_5 L195 IO_L18P_5 E175 IO_L18N_5 F175 IO_L19P_5 J235 IO_L19N_5 K235 IO_L20P_5 D185 IO_L20N_VREF_5 E185 IO_L21P_5 K215 IO_L21N_5 J215 IO_L22P_5 C185 IO_L22N_5 C175 IO_L23P_VRN_5 J245 IO_L23N_VRP_5 H235 IO_L24P_CC_LC_5 A175 IO_L24N_CC_LC_5 B175 IO_L9P_CC_LC_5 D245 IO_L9N_CC_LC_5 C245 IO_L10P_5 D215 IO_L10N_5 C215 IO_L11P_5 F245 IO_L11N_5 F235 IO_L12P_5 C235 IO_L12N_VREF_5 C225 IO_L13P_5 H225 IO_L13N_5 G225 IO_L14P_5 G175 IO_L14N_5 H175 IO_L15P_5 H245 IO_L15N_5 G245 IO_L16P_5 C195 IO_L16N_5 D195 IO_L25P_CC_LC_5 K225 IO_L25N_CC_LC_5 L235 IO_L26P_5 L185 IO_L26N_5 K185 IO_L27P_5 L2454 www.xilinx.com Virtex-4 FPGA Packaging and Pinout SpecificationUG075 (v3.3) September 19, 2008

RFF672 Flip-Chip Fine-Pitch BGA PackageTable 2-3: FF672 Package — FX60, FX40, and FX20 Devices (Continued)Bank Pin Description Pin Number No Connects in FX20 Devices5 IO_L27N_5 M245 IO_L28P_5 D165 IO_L28N_VREF_5 E165 IO_L29P_5 M225 IO_L29N_5 N225 IO_L30P_5 B165 IO_L30N_5 C165 IO_L31P_5 N245 IO_L31N_5 N235 IO_L32P_5 A155 IO_L32N_5 B156 IO_L1P_6 H86 IO_L1N_6 H76 IO_L2P_6 A86 IO_L2N_6 A76 IO_L3P_6 F86 IO_L3N_6 F76 IO_L4P_6 G76 IO_L4N_VREF_6 H66 IO_L5P_6 E86 IO_L5N_6 E76 IO_L6P_6 B76 IO_L6N_6 C76 IO_L7P_6 D86 IO_L7N_6 C86 IO_L8P_CC_LC_6 D66 IO_L8N_CC_LC_6 E66 IO_L17P_6 B96 IO_L17N_6 A96 IO_L18P_6 C36 IO_L18N_6 D36 IO_L19P_6 G106 IO_L19N_6 F106 IO_L20P_6 E36 IO_L20N_VREF_6 F36 IO_L21P_6 E10Virtex-4 FPGA Packaging and Pinout Specification www.xilinx.com 55UG075 (v3.3) September 19, 2008

Chapter 2: Pinout TablesRTable 2-3: FF672 Package — FX60, FX40, and FX20 Devices (Continued)Bank Pin Description Pin Number No Connects in FX20 Devices6 IO_L21N_6 D106 IO_L22P_6 K66 IO_L22N_6 J56 IO_L23P_VRN_6 B106 IO_L23N_VRP_6 A106 IO_L24P_CC_LC_6 H46 IO_L24N_CC_LC_6 G46 IO_L9P_CC_LC_6 J96 IO_L9N_CC_LC_6 K106 IO_L10P_6 B66 IO_L10N_6 C66 IO_L11P_6 H96 IO_L11N_6 G96 IO_L12P_6 D56 IO_L12N_VREF_6 E56 IO_L13P_6 D96 IO_L13N_6 C96 IO_L14P_6 C46 IO_L14N_6 D46 IO_L15P_6 K86 IO_L15N_6 K76 IO_L16P_6 G56 IO_L16N_6 F46 IO_L25P_CC_LC_6 E116 IO_L25N_CC_LC_6 D116 IO_L26P_6 L76 IO_L26N_6 M66 IO_L27P_6 C116 IO_L27N_6 B116 IO_L28P_6 J46 IO_L28N_VREF_6 H36 IO_L29P_6 G126 IO_L29N_6 G116 IO_L30P_6 K36 IO_L30N_6 J36 IO_L31P_6 L106 IO_L31N_6 L96 IO_L32P_6 M556 www.xilinx.com Virtex-4 FPGA Packaging and Pinout SpecificationUG075 (v3.3) September 19, 2008

RFF672 Flip-Chip Fine-Pitch BGA PackageTable 2-3: FF672 Package — FX60, FX40, and FX20 Devices (Continued)Bank Pin Description Pin Number No Connects in FX20 Devices6 IO_L32N_6 L57 IO_L25P_CC_SM7_LC_7 AB247 IO_L25N_CC_SM7_LC_7 AC247 IO_L26P_SM6_7 AB207 IO_L26N_SM6_7 AB197 IO_L27P_SM5_7 W207 IO_L27N_SM5_7 W197 IO_L28P_7 W187 IO_L28N_VREF_7 V187 IO_L29P_SM4_7 AD247 IO_L29N_SM4_7 AD237 IO_L30P_SM3_7 AA207 IO_L30N_SM3_7 AA197 IO_L31P_SM2_7 AC237 IO_L31N_SM2_7 AC227 IO_L32P_SM1_7 AB227 IO_L32N_SM1_7 AB217 IO_L17P_7 V217 IO_L17N_7 U217 IO_L18P_7 AC197 IO_L18N_7 AC187 IO_L19P_7 AA247 IO_L19N_7 AA237 IO_L20P_7 AA187 IO_L20N_VREF_7 Y187 IO_L21P_7 Y227 IO_L21N_7 AA227 IO_L22P_7 AD207 IO_L22N_7 AD197 IO_L23P_VRN_7 W217 IO_L23N_VRP_7 Y207 IO_L24P_CC_LC_7 AC217 IO_L24N_CC_LC_7 AD217 IO_L1P_7 P247 IO_L1N_7 R237 IO_L2P_7 AB15Virtex-4 FPGA Packaging and Pinout Specification www.xilinx.com 57UG075 (v3.3) September 19, 2008

Chapter 2: Pinout TablesRTable 2-3: FF672 Package — FX60, FX40, and FX20 Devices (Continued)Bank Pin Description Pin Number No Connects in FX20 Devices7 IO_L2N_7 AA157 IO_L3P_7 R217 IO_L3N_7 R207 IO_L4P_7 AD167 IO_L4N_VREF_7 AC167 IO_L5P_7 T237 IO_L5N_7 T227 IO_L6P_7 T177 IO_L6N_7 U177 IO_L7P_7 U247 IO_L7N_7 T247 IO_L8P_CC_LC_7 Y167 IO_L8N_CC_LC_7 Y157 IO_L9P_CC_LC_7 W247 IO_L9N_CC_LC_7 V247 IO_L10P_7 AB177 IO_L10N_7 AB167 IO_L11P_7 V237 IO_L11N_7 V227 IO_L12P_7 U197 IO_L12N_VREF_7 T187 IO_L13P_7 W237 IO_L13N_7 Y237 IO_L14P_7 AA177 IO_L14N_7 Y177 IO_L15P_7 U207 IO_L15N_7 T207 IO_L16P_7 AD187 IO_L16N_7 AC178 IO_L25P_CC_LC_8 AC78 IO_L25N_CC_LC_8 AC68 IO_L26P_8 Y68 IO_L26N_8 AA58 IO_L27P_8 Y88 IO_L27N_8 AA88 IO_L28P_8 AB558 www.xilinx.com Virtex-4 FPGA Packaging and Pinout SpecificationUG075 (v3.3) September 19, 2008

RFF672 Flip-Chip Fine-Pitch BGA PackageTable 2-3: FF672 Package — FX60, FX40, and FX20 Devices (Continued)Bank Pin Description Pin Number No Connects in FX20 Devices8 IO_L28N_VREF_8 AB48 IO_L29P_8 AB78 IO_L29N_8 AB68 IO_L30P_8 AD48 IO_L30N_8 AD38 IO_L31P_8 AA78 IO_L31N_8 Y78 IO_L32P_8 AD68 IO_L32N_8 AD58 IO_L17P_8 AD98 IO_L17N_8 AD88 IO_L18P_8 Y38 IO_L18N_8 W48 IO_L19P_8 AC98 IO_L19N_8 AC88 IO_L20P_8 AA48 IO_L20N_VREF_8 AA38 IO_L21P_8 AA98 IO_L21N_8 AB98 IO_L22P_8 Y58 IO_L22N_8 W58 IO_L23P_VRN_8 W98 IO_L23N_VRP_8 W88 IO_L24P_CC_LC_8 AC48 IO_L24N_CC_LC_8 AC38 IO_L1P_8 AD118 IO_L1N_8 AD108 IO_L2P_8 L48 IO_L2N_8 L38 IO_L3P_8 AB118 IO_L3N_8 AC118 IO_L4P_8 M48 IO_L4N_VREF_8 N48 IO_L5P_8 T98 IO_L5N_8 T88 IO_L6P_8 P58 IO_L6N_8 R58 IO_L7P_8 AA10Virtex-4 FPGA Packaging and Pinout Specification www.xilinx.com 59UG075 (v3.3) September 19, 2008

Chapter 2: Pinout TablesRTable 2-3: FF672 Package — FX60, FX40, and FX20 Devices (Continued)Bank Pin Description Pin Number No Connects in FX20 Devices8 IO_L7N_8 AB108 IO_L8P_CC_LC_8 P48 IO_L8N_CC_LC_8 R38 IO_L9P_CC_LC_8 W108 IO_L9N_CC_LC_8 Y108 IO_L10P_8 N38 IO_L10N_8 P38 IO_L11P_8 U68 IO_L11N_8 U58 IO_L12P_8 T48 IO_L12N_VREF_8 T38 IO_L13P_8 U78 IO_L13N_8 V68 IO_L14P_8 U48 IO_L14N_8 V48 IO_L15P_8 U98 IO_L15N_8 V88 IO_L16P_8 V38 IO_L16N_8 W39 IO_L17P_9 M20 NC9 IO_L17N_9 M19 NC9 IO_L18P_9 P16 NC9 IO_L18N_9 N16 NC9 IO_L19P_9 N21 NC9 IO_L19N_9 M21 NC9 IO_L20P_9 N18 NC9 IO_L20N_VREF_9 N17 NC9 IO_L21P_9 P19 NC9 IO_L21N_9 N19 NC9 IO_L22P_9 R17 NC9 IO_L22N_9 R16 NC9 IO_L23P_VRN_9 P21 NC9 IO_L23N_VRP_9 P20 NC9 IO_L24P_CC_LC_9 R18 NC9 IO_L24N_CC_LC_9 P18 NC60 www.xilinx.com Virtex-4 FPGA Packaging and Pinout SpecificationUG075 (v3.3) September 19, 2008

RFF672 Flip-Chip Fine-Pitch BGA PackageTable 2-3: FF672 Package — FX60, FX40, and FX20 Devices (Continued)Bank Pin Description Pin Number No Connects in FX20 Devices10 IO_L17P_10 M10 NC10 IO_L17N_10 M9 NC10 IO_L18P_10 N8 NC10 IO_L18N_10 N7 NC10 IO_L19P_10 M11 NC10 IO_L19N_10 N11 NC10 IO_L20P_10 P8 NC10 IO_L20N_VREF_10 R8 NC10 IO_L21P_10 P11 NC10 IO_L21N_10 P10 NC10 IO_L22P_10 P6 NC10 IO_L22N_10 N6 NC10 IO_L23P_VRN_10 N9 NC10 IO_L23N_VRP_10 P9 NC10 IO_L24P_CC_LC_10 R7 NC10 IO_L24N_CC_LC_10 R6 NC0 VCCO_0 (1) T110 VCCO_0 (1) M130 VCCO_0 (1) R140 VCCO_0 (1) L161 VCCO_1 J121 VCCO_1 H152 VCCO_2 V152 VCCO_2 W123 VCCO_3 B133 VCCO_3 E144 VCCO_4 AB134 VCCO_4 AE145 VCCO_5 A165 VCCO_5 D175 VCCO_5 G185 VCCO_5 K195 VCCO_5 C205 VCCO_5 F215 VCCO_5 J225 VCCO_5 M23Virtex-4 FPGA Packaging and Pinout Specification www.xilinx.com 61UG075 (v3.3) September 19, 2008

Chapter 2: Pinout TablesRTable 2-3: FF672 Package — FX60, FX40, and FX20 Devices (Continued)Bank Pin Description Pin Number No Connects in FX20 Devices5 VCCO_5 E246 VCCO_6 E46 VCCO_6 H56 VCCO_6 A66 VCCO_6 L66 VCCO_6 D76 VCCO_6 G86 VCCO_6 K96 VCCO_6 C106 VCCO_6 F117 VCCO_7 AA167 VCCO_7 AD177 VCCO_7 U187 VCCO_7 Y197 VCCO_7 AC207 VCCO_7 T217 VCCO_7 W227 VCCO_7 AB237 VCCO_7 R248 VCCO_8 M38 VCCO_8 AB38 VCCO_8 R48 VCCO_8 V58 VCCO_8 AA68 VCCO_8 AD78 VCCO_8 U88 VCCO_8 Y98 VCCO_8 AC109 VCCO_9 P17 NC9 VCCO_9 N20 NC10 VCCO_10 P7 NC10 VCCO_10 N10 NCN/A AVCCAUXRXA_102 B20N/A RXPPADA_102 A19N/A VTRXA_102 A21N/A RXNPADA_102 A2062 www.xilinx.com Virtex-4 FPGA Packaging and Pinout SpecificationUG075 (v3.3) September 19, 2008

RFF672 Flip-Chip Fine-Pitch BGA PackageTable 2-3: FF672 Package — FX60, FX40, and FX20 Devices (Continued)Bank Pin Description Pin Number No Connects in FX20 DevicesN/A AVCCAUXMGT_102 C25N/A AVCCAUXTX_102 B23N/A VTTXA_102 B22N/A TXPPADA_102 A22N/A TXNPADA_102 A23N/A VTTXB_102 B24N/A TXPPADB_102 A24N/A TXNPADB_102 A25N/A RXPPADB_102 C26N/A VTRXB_102 B26N/A AVCCAUXRXB_102 D25N/A RXNPADB_102 D26N/A MGTCLK_P_102 F26N/A MGTCLK_N_102 G26N/A AVCCAUXRXA_103 K25 NCN/A RXPPADA_103 J26 NCN/A VTRXA_103 L26 NCN/A RXNPADA_103 K26 NCN/A AVCCAUXTX_103 P25 NCN/A VTTXA_103 M25 NCN/A TXPPADA_103 M26 NCN/A TXNPADA_103 N26 NCN/A VTTXB_103 R25 NCN/A TXPPADB_103 P26 NCN/A AVCCAUXMGT_103 U25 NCN/A TXNPADB_103 R26 NCN/A RXPPADB_103 U26 NCN/A VTRXB_103 T26 NCN/A AVCCAUXRXB_103 V25 NCN/A RXNPADB_103 V26 NCN/A AVCCAUXRXA_105 Y25N/A RXPPADA_105 W26N/A VTRXA_105 AA26N/A RXNPADA_105 Y26N/A AVCCAUXMGT_105 AE24N/A AVCCAUXTX_105 AC25N/A VTTXA_105 AB25N/A TXPPADA_105 AB26Virtex-4 FPGA Packaging and Pinout Specification www.xilinx.com 63UG075 (v3.3) September 19, 2008

Chapter 2: Pinout TablesRTable 2-3: FF672 Package — FX60, FX40, and FX20 Devices (Continued)Bank Pin Description Pin Number No Connects in FX20 DevicesN/A TXNPADA_105 AC26N/A VTTXB_105 AD25N/A TXPPADB_105 AD26N/A TXNPADB_105 AE26N/A AVCCAUXRXB_105 AE23N/A RXPPADB_105 AF24N/A VTRXB_105 AF25N/A RXNPADB_105 AF23N/A MGTCLK_P_105 AF21N/A MGTCLK_N_105 AF20N/A RTERM_105 AE21N/A MGTVREF_105 AE19N/A AVCCAUXRXA_110 AD2N/A RXPPADA_110 AC1N/A VTRXA_110 AE1N/A RXNPADA_110 AD1N/A AVCCAUXMGT_110 AE7N/A AVCCAUXTX_110 AE4N/A VTTXA_110 AE2N/A TXPPADA_110 AF2N/A TXNPADA_110 AF3N/A VTTXB_110 AE5N/A TXPPADB_110 AF4N/A TXNPADB_110 AF5N/A AVCCAUXRXB_110 AE8N/A RXPPADB_110 AF7N/A VTRXB_110 AF6N/A RXNPADB_110 AF8N/A MGTCLK_P_110 AF10N/A MGTCLK_N_110 AF11N/A RTERM_110 AE10N/A MGTVREF_110 AE12N/A AVCCAUXRXA_112 P2 NCN/A RXPPADA_112 N1 NCN/A VTRXA_112 R1 NCN/A RXNPADA_112 P1 NCN/A AVCCAUXMGT_112 AA2 NCN/A AVCCAUXTX_112 V2 NC64 www.xilinx.com Virtex-4 FPGA Packaging and Pinout SpecificationUG075 (v3.3) September 19, 2008

RFF672 Flip-Chip Fine-Pitch BGA PackageTable 2-3: FF672 Package — FX60, FX40, and FX20 Devices (Continued)Bank Pin Description Pin Number No Connects in FX20 DevicesN/A VTTXA_112 T2 NCN/A TXPPADA_112 T1 NCN/A TXNPADA_112 U1 NCN/A VTTXB_112 W2 NCN/A TXPPADB_112 V1 NCN/A TXNPADB_112 W1 NCN/A AVCCAUXRXB_112 AB2 NCN/A RXPPADB_112 AA1 NCN/A VTRXB_112 Y1 NCN/A RXNPADB_112 AB1 NCN/A AVCCAUXRXA_113 B4N/A RXPPADA_113 A4N/A VTRXA_113 A2N/A RXNPADA_113 A3N/A AVCCAUXMGT_113 G2N/A AVCCAUXTX_113 D2N/A VTTXA_113 C2N/A TXPPADA_113 B1N/A TXNPADA_113 C1N/A VTTXB_113 E2N/A TXPPADB_113 D1N/A TXNPADB_113 E1N/A AVCCAUXRXB_113 H2N/A RXPPADB_113 G1N/A VTRXB_113 F1N/A RXNPADB_113 H1N/A MGTCLK_P_113 K1N/A MGTCLK_N_113 L1N/A GNDA_102 A18N/A GNDA_102 B19N/A GNDA_102 B21N/A GNDA_102 B25N/A GNDA_102 E25N/A GNDA_102 H25N/A GNDA_102 E26N/A GNDA_102 H26Virtex-4 FPGA Packaging and Pinout Specification www.xilinx.com 65UG075 (v3.3) September 19, 2008

Chapter 2: Pinout TablesRTable 2-3: FF672 Package — FX60, FX40, and FX20 Devices (Continued)Bank Pin Description Pin Number No Connects in FX20 DevicesN/A GNDA_103 J25 NCN/A GNDA_103 L25 NCN/A GNDA_103 N25 NCN/A GNDA_103 T25 NCN/A GNDA_105 AF19N/A GNDA_105 AE20N/A GNDA_105 AE22N/A GNDA_105 AF22N/A GNDA_105 W25N/A GNDA_105 AA25N/A GNDA_105 AE25N/A GNDA_110 AC2N/A GNDA_110 AE3N/A GNDA_110 AE6N/A GNDA_110 AE9N/A GNDA_110 AF9N/A GNDA_110 AE11N/A GNDA_110 AF12N/A GNDA_112 N2 NCN/A GNDA_112 R2 NCN/A GNDA_112 U2 NCN/A GNDA_112 Y2 NCN/A GNDA_113 J1N/A GNDA_113 M1N/A GNDA_113 B2N/A GNDA_113 F2N/A GNDA_113 J2N/A GNDA_113 K2N/A GNDA_113 L2N/A GNDA_113 M2N/A GNDA_113 B3N/A GNDA_113 A5N/A GNDA_113 B5N/A VREFN_SM (2) AE18 NCN/A VREFP_SM (2) AE17 NCN/A AVDD_SM (3) AE16 NC66 www.xilinx.com Virtex-4 FPGA Packaging and Pinout SpecificationUG075 (v3.3) September 19, 2008

RFF672 Flip-Chip Fine-Pitch BGA PackageTable 2-3: FF672 Package — FX60, FX40, and FX20 Devices (Continued)Bank Pin Description Pin Number No Connects in FX20 DevicesN/A VN_SM (2) AF18 NCN/A VP_SM (2) AF17 NCN/A AVSS_SM (2) AF16 NCN/A GND G3N/A GND U3N/A GND K4N/A GND Y4N/A GND C5N/A GND N5N/A GND AC5N/A GND F6N/A GND T6N/A GND J7N/A GND W7N/A GND B8N/A GND M8N/A GND AB8N/A GND E9N/A GND R9N/A GND H10N/A GND V10N/A GND A11N/A GND L11N/A GND AA11N/A GND D12N/A GND P12N/A GND T12N/A GND AD12N/A GND G13N/A GND N13N/A GND U13N/A GND K14N/A GND Y14N/A GND C15N/A GND N15N/A GND AC15Virtex-4 FPGA Packaging and Pinout Specification www.xilinx.com 67UG075 (v3.3) September 19, 2008

Chapter 2: Pinout TablesRTable 2-3: FF672 Package — FX60, FX40, and FX20 Devices (Continued)Bank Pin Description Pin Number No Connects in FX20 DevicesN/A GND F16N/A GND T16N/A GND J17N/A GND W17N/A GND B18N/A GND M18N/A GND AB18N/A GND E19N/A GND R19N/A GND H20N/A GND V20N/A GND L21N/A GND AA21N/A GND D22N/A GND P22N/A GND AD22N/A GND G23N/A GND U23N/A GND K24N/A GND Y24N/A VCCAUX F5N/A VCCAUX T5N/A VCCAUX J6N/A VCCAUX W6N/A VCCAUX M7N/A VCCAUX N12N/A VCCAUX P15N/A VCCAUX H21N/A VCCAUX L22N/A VCCAUX P23N/A VCCAUX F25N/A VCCAUX G25N/A VCCINT K5N/A VCCINT G6N/A VCCINT T7N/A VCCINT V768 www.xilinx.com Virtex-4 FPGA Packaging and Pinout SpecificationUG075 (v3.3) September 19, 2008

RFF672 Flip-Chip Fine-Pitch BGA PackageTable 2-3: FF672 Package — FX60, FX40, and FX20 Devices (Continued)Bank Pin Description Pin Number No Connects in FX20 DevicesN/A VCCINT J8N/A VCCINT L8N/A VCCINT F9N/A VCCINT V9N/A VCCINT J10N/A VCCINT R10N/A VCCINT L12N/A VCCINT R12N/A VCCINT P13N/A VCCINT T13N/A VCCINT L14N/A VCCINT N14N/A VCCINT M15N/A VCCINT T15N/A VCCINT M17N/A VCCINT V17N/A VCCINT J18N/A VCCINT T19N/A VCCINT V19N/A VCCINT J20N/A VCCINT L20N/A VCCINT Y21N/A VCCINT R22N/A VCCINT U22Notes:1. This voltage is also referred to as V CC_CONFIG in the Virtex-4 Configuration Guide.2. Connect this reserved pin to GND.3. Connect this reserved pin to 2.5V (sharing the same PCB supply distribution as V CCAUX is acceptable).Virtex-4 FPGA Packaging and Pinout Specification www.xilinx.com 69UG075 (v3.3) September 19, 2008

Chapter 2: Pinout TablesRFF676 Flip-Chip Fine-Pitch BGA PackageAs shown in Table 2-4, Virtex-4 XC4VLX15 and XC4VLX25 devices are available in theFF676 flip-chip fine-pitch BGA package.The “No Connect” column in Table 2-4 shows pins that are not available in LX15 devices.To be assured of having the very latest Virtex-4 FPGA pinout information, visitwww.xilinx.com and check for any updates to this document. ASCII package pinout filesare also available for download from the Xilinx website.Table 2-4: FF676 Package — LX15 and LX25 DevicesBank Pin Description Pin Number0 HSWAPEN_0 K160 CCLK_0 M140 D_IN_0 L130 PROG_B_0 K170 INIT_B_0 K150 CS_B_0 M120 DONE_0 L150 RDWR_B_0 R110 VBATT_0 L170 M2_0 M160 PWRDWN_B_0 U120 TMS_0 T100 M0_0 P140 TDO_0 R130 TCK_0 U100 M1_0 R150 DOUT_BUSY_0 T140 TDI_0 U110 TDN_0 F120 TDP_0 E12No Connects inLX15 Devices1 IO_L1P_D31_LC_1 J141 IO_L1N_D30_LC_1 H141 IO_L2P_D29_LC_1 J131 IO_L2N_D28_LC_1 H131 IO_L3P_D27_LC_1 J161 IO_L3N_D26_LC_1 J151 IO_L4P_D25_LC_1 K131 IO_L4N_D24_VREF_LC_1 K121 IO_L5P_D23_LC_1 G1570 www.xilinx.com Virtex-4 FPGA Packaging and Pinout SpecificationUG075 (v3.3) September 19, 2008

RFF676 Flip-Chip Fine-Pitch BGA PackageTable 2-4: FF676 Package — LX15 and LX25 Devices (Continued)Bank Pin Description Pin Number1 IO_L5N_D22_LC_1 G141 IO_L6P_D21_LC_1 H121 IO_L6N_D20_LC_1 H111 IO_L7P_D19_LC_1 H161 IO_L7N_D18_LC_1 G161 IO_L8P_D17_CC_LC_1 J111 IO_L8N_D16_CC_LC_1 K11No Connects inLX15 Devices2 IO_L1P_D15_CC_LC_2 U162 IO_L1N_D14_CC_LC_2 V162 IO_L2P_D13_LC_2 Y112 IO_L2N_D12_LC_2 W112 IO_L3P_D11_LC_2 W162 IO_L3N_D10_LC_2 W152 IO_L4P_D9_LC_2 V122 IO_L4N_D8_VREF_LC_2 V112 IO_L5P_D7_LC_2 U152 IO_L5N_D6_LC_2 U142 IO_L6P_D5_LC_2 Y132 IO_L6N_D4_LC_2 Y122 IO_L7P_D3_LC_2 V142 IO_L7N_D2_LC_2 W142 IO_L8P_D1_LC_2 W132 IO_L8N_D0_LC_2 V133 IO_L1P_GC_CC_LC_3 A143 IO_L1N_GC_CC_LC_3 B143 IO_L2P_GC_VRN_LC_3 C133 IO_L2N_GC_VRP_LC_3 D133 IO_L3P_GC_LC_3 D143 IO_L3N_GC_LC_3 C143 IO_L4P_GC_LC_3 E133 IO_L4N_GC_VREF_LC_3 F133 IO_L5P_GC_LC_3 E153 IO_L5N_GC_LC_3 D153 IO_L6P_GC_LC_3 B123 IO_L6N_GC_LC_3 C12Virtex-4 FPGA Packaging and Pinout Specification www.xilinx.com 71UG075 (v3.3) September 19, 2008

Chapter 2: Pinout TablesRTable 2-4: FF676 Package — LX15 and LX25 Devices (Continued)Bank Pin Description Pin Number3 IO_L7P_GC_LC_3 F153 IO_L7N_GC_LC_3 F143 IO_L8P_GC_LC_3 A133 IO_L8N_GC_LC_3 A12No Connects inLX15 Devices4 IO_L1P_GC_LC_4 AA144 IO_L1N_GC_LC_4 AA134 IO_L2P_GC_LC_4 AB124 IO_L2N_GC_LC_4 AA124 IO_L3P_GC_LC_4 AB144 IO_L3N_GC_LC_4 AC144 IO_L4P_GC_LC_4 AC134 IO_L4N_GC_VREF_LC_4 AC124 IO_L5P_GC_LC_4 AD154 IO_L5N_GC_LC_4 AD144 IO_L6P_GC_LC_4 AD134 IO_L6N_GC_LC_4 AE134 IO_L7P_GC_VRN_LC_4 AE154 IO_L7N_GC_VRP_LC_4 AF154 IO_L8P_GC_CC_LC_4 AF144 IO_L8N_GC_CC_LC_4 AF135 IO_L1P_5 B155 IO_L1N_5 A155 IO_L2P_5 C165 IO_L2N_5 B165 IO_L3P_5 D165 IO_L3N_5 C175 IO_L4P_5 H175 IO_L4N_VREF_5 G175 IO_L5P_5 B175 IO_L5N_5 A175 IO_L6P_5 E175 IO_L6N_5 F175 IO_L7P_5 A185 IO_L7N_5 A195 IO_L8P_CC_LC_5 C1872 www.xilinx.com Virtex-4 FPGA Packaging and Pinout SpecificationUG075 (v3.3) September 19, 2008

RFF676 Flip-Chip Fine-Pitch BGA PackageTable 2-4: FF676 Package — LX15 and LX25 Devices (Continued)Bank Pin Description Pin Number5 IO_L8N_CC_LC_5 C195 IO_L17P_5 G195 IO_L17N_5 G205 IO_L18P_5 A225 IO_L18N_5 A235 IO_L19P_5 B225 IO_L19N_5 C225 IO_L20P_5 J205 IO_L20N_VREF_5 K205 IO_L21P_5 K185 IO_L21N_5 L195 IO_L22P_5 E225 IO_L22N_5 F225 IO_L23P_VRN_5 E235 IO_L23N_VRP_5 F235 IO_L24P_CC_LC_5 C235 IO_L24N_CC_LC_5 D235 IO_L9P_CC_LC_5 D185 IO_L9N_CC_LC_5 D195 IO_L10P_5 F185 IO_L10N_5 E185 IO_L11P_5 B195 IO_L11N_5 A205 IO_L12P_5 H185 IO_L12N_VREF_5 J195 IO_L13P_5 B205 IO_L13N_5 B215 IO_L14P_5 D205 IO_L14N_5 C215 IO_L15P_5 D215 IO_L15N_5 E215 IO_L16P_5 E205 IO_L16N_5 F205 IO_L25P_CC_LC_5 A245 IO_L25N_CC_LC_5 B245 IO_L26P_5 C245 IO_L26N_5 D24No Connects inLX15 DevicesVirtex-4 FPGA Packaging and Pinout Specification www.xilinx.com 73UG075 (v3.3) September 19, 2008

Chapter 2: Pinout TablesRTable 2-4: FF676 Package — LX15 and LX25 Devices (Continued)Bank Pin Description Pin Number5 IO_L27P_5 A255 IO_L27N_5 B255 IO_L28P_5 G215 IO_L28N_VREF_5 G225 IO_L29P_5 B265 IO_L29N_5 C265 IO_L30P_5 D255 IO_L30N_5 D265 IO_L31P_5 E255 IO_L31N_5 E265 IO_L32P_5 F245 IO_L32N_5 F25No Connects inLX15 Devices6 IO_L1P_6 G116 IO_L1N_6 F106 IO_L2P_6 E116 IO_L2N_6 E106 IO_L3P_6 D116 IO_L3N_6 D106 IO_L4P_6 G96 IO_L4N_VREF_6 H96 IO_L5P_6 C116 IO_L5N_6 B116 IO_L6P_6 B106 IO_L6N_6 A106 IO_L7P_6 A96 IO_L7N_6 A86 IO_L8P_CC_LC_6 C96 IO_L8N_CC_LC_6 B96 IO_L17P_6 F86 IO_L17N_6 E76 IO_L18P_6 B46 IO_L18N_6 C46 IO_L19P_6 E66 IO_L19N_6 F76 IO_L20P_6 J86 IO_L20N_VREF_6 K874 www.xilinx.com Virtex-4 FPGA Packaging and Pinout SpecificationUG075 (v3.3) September 19, 2008

RFF676 Flip-Chip Fine-Pitch BGA PackageTable 2-4: FF676 Package — LX15 and LX25 Devices (Continued)Bank Pin Description Pin Number6 IO_L21P_6 E56 IO_L21N_6 D56 IO_L22P_6 A26 IO_L22N_6 B16 IO_L23P_VRN_6 G76 IO_L23N_VRP_6 G66 IO_L24P_CC_LC_6 C36 IO_L24N_CC_LC_6 C26 IO_L9P_CC_LC_6 D96 IO_L9N_CC_LC_6 C86 IO_L10P_6 A76 IO_L10N_6 B76 IO_L11P_6 C76 IO_L11N_6 B66 IO_L12P_6 J96 IO_L12N_VREF_6 H86 IO_L13P_6 A56 IO_L13N_6 B56 IO_L14P_6 D86 IO_L14N_6 E86 IO_L15P_6 A46 IO_L15N_6 A36 IO_L16P_6 C66 IO_L16N_6 D66 IO_L25P_CC_LC_6 D46 IO_L25N_CC_LC_6 D36 IO_L26P_6 F56 IO_L26N_6 F46 IO_L27P_6 B26 IO_L27N_6 C16 IO_L28P_6 K106 IO_L28N_VREF_6 L96 IO_L29P_6 E36 IO_L29N_6 F36 IO_L30P_6 H66 IO_L30N_6 G56 IO_L31P_6 G4No Connects inLX15 DevicesVirtex-4 FPGA Packaging and Pinout Specification www.xilinx.com 75UG075 (v3.3) September 19, 2008

Chapter 2: Pinout TablesRTable 2-4: FF676 Package — LX15 and LX25 Devices (Continued)Bank Pin Description Pin Number6 IO_L31N_6 H46 IO_L32P_6 J66 IO_L32N_6 J5No Connects inLX15 Devices7 IO_L25P_CC_SM7_LC_7 AB167 IO_L25N_CC_SM7_LC_7 AA177 IO_L26P_SM6_7 AF207 IO_L26N_SM6_7 AE207 IO_L27P_SM5_7 Y167 IO_L27N_SM5_7 Y177 IO_L28P_7 V177 IO_L28N_VREF_7 U177 IO_L29P_SM4_7 AB177 IO_L29N_SM4_7 AA187 IO_L30P_SM3_7 AD187 IO_L30N_SM3_7 AD197 IO_L31P_SM2_7 AC167 IO_L31N_SM2_7 AD167 IO_L32P_SM1_7 AC177 IO_L32N_SM1_7 AC187 IO_L17P_7 AF227 IO_L17N_7 AF237 IO_L18P_7 AA207 IO_L18N_7 AB217 IO_L19P_7 Y187 IO_L19N_7 AA197 IO_L20P_7 W187 IO_L20N_VREF_7 V187 IO_L21P_7 AE217 IO_L21N_7 AE227 IO_L22P_7 AD207 IO_L22N_7 AD217 IO_L23P_VRN_7 AA157 IO_L23N_VRP_7 AB157 IO_L24P_CC_LC_7 AC197 IO_L24N_CC_LC_7 AB197 IO_L1P_7 V2176 www.xilinx.com Virtex-4 FPGA Packaging and Pinout SpecificationUG075 (v3.3) September 19, 2008

RFF676 Flip-Chip Fine-Pitch BGA PackageTable 2-4: FF676 Package — LX15 and LX25 Devices (Continued)Bank Pin Description Pin Number7 IO_L1N_7 V227 IO_L2P_7 Y237 IO_L2N_7 W237 IO_L3P_7 AA237 IO_L3N_7 AA247 IO_L4P_7 T187 IO_L4N_VREF_7 T197 IO_L5P_7 Y227 IO_L5N_7 W217 IO_L6P_7 AE257 IO_L6N_7 AD257 IO_L7P_7 AE267 IO_L7N_7 AD267 IO_L8P_CC_LC_7 AC247 IO_L8N_CC_LC_7 AB247 IO_L9P_CC_LC_7 AC237 IO_L9N_CC_LC_7 AD247 IO_L10P_7 AF247 IO_L10N_7 AF257 IO_L11P_7 AC227 IO_L11N_7 AB227 IO_L12P_7 V197 IO_L12N_VREF_7 U197 IO_L13P_7 W197 IO_L13N_7 Y207 IO_L14P_7 Y217 IO_L14N_7 AA227 IO_L15P_7 AE237 IO_L15N_7 AD237 IO_L16P_7 AB207 IO_L16N_7 AC21No Connects inLX15 Devices8 IO_L25P_CC_LC_8 AF88 IO_L25N_CC_LC_8 AE88 IO_L26P_8 AD108 IO_L26N_8 AD98 IO_L27P_8 AE10Virtex-4 FPGA Packaging and Pinout Specification www.xilinx.com 77UG075 (v3.3) September 19, 2008

Chapter 2: Pinout TablesRTable 2-4: FF676 Package — LX15 and LX25 Devices (Continued)Bank Pin Description Pin Number8 IO_L27N_8 AF98 IO_L28P_8 W108 IO_L28N_VREF_8 Y108 IO_L29P_8 AA108 IO_L29N_8 AB108 IO_L30P_8 AE118 IO_L30N_8 AF108 IO_L31P_8 AE128 IO_L31N_8 AF128 IO_L32P_8 AC118 IO_L32N_8 AD118 IO_L17P_8 AC68 IO_L17N_8 AB68 IO_L18P_8 AE68 IO_L18N_8 AD68 IO_L19P_8 AB78 IO_L19N_8 AA78 IO_L20P_8 W98 IO_L20N_VREF_8 V88 IO_L21P_8 AC88 IO_L21N_8 AC78 IO_L22P_8 AF78 IO_L22N_8 AE78 IO_L23P_VRN_8 AB98 IO_L23N_VRP_8 AA98 IO_L24P_CC_LC_8 AC98 IO_L24N_CC_LC_8 AD88 IO_L1P_8 AB18 IO_L1N_8 AA28 IO_L2P_8 AB28 IO_L2N_8 AA38 IO_L3P_8 AC28 IO_L3N_8 AC18 IO_L4P_8 V78 IO_L4N_VREF_8 U78 IO_L5P_8 AA48 IO_L5N_8 Y5No Connects inLX15 Devices78 www.xilinx.com Virtex-4 FPGA Packaging and Pinout SpecificationUG075 (v3.3) September 19, 2008

RFF676 Flip-Chip Fine-Pitch BGA PackageTable 2-4: FF676 Package — LX15 and LX25 Devices (Continued)Bank Pin Description Pin Number8 IO_L6P_8 Y68 IO_L6N_8 AA58 IO_L7P_8 AB48 IO_L7N_8 AC38 IO_L8P_CC_LC_8 AE18 IO_L8N_CC_LC_8 AD18 IO_L9P_CC_LC_8 AF38 IO_L9N_CC_LC_8 AF48 IO_L10P_8 AB58 IO_L10N_8 AC48 IO_L11P_8 AD38 IO_L11N_8 AE28 IO_L12P_8 U98 IO_L12N_VREF_8 T88 IO_L13P_8 AE38 IO_L13N_8 AF28 IO_L14P_8 AD58 IO_L14N_8 AD48 IO_L15P_8 Y88 IO_L15N_8 Y78 IO_L16P_8 AF58 IO_L16N_8 AE5No Connects inLX15 Devices9 IO_L17P_9 N24 NC9 IO_L17N_9 P23 NC9 IO_L18P_9 P24 NC9 IO_L18N_9 P25 NC9 IO_L19P_9 R26 NC9 IO_L19N_9 P26 NC9 IO_L20P_9 R20 NC9 IO_L20N_VREF_9 R21 NC9 IO_L21P_9 R22 NC9 IO_L21N_9 R23 NC9 IO_L22P_9 T25 NC9 IO_L22N_9 R25 NC9 IO_L23P_VRN_9 T23 NC9 IO_L23N_VRP_9 T24 NCVirtex-4 FPGA Packaging and Pinout Specification www.xilinx.com 79UG075 (v3.3) September 19, 2008

Chapter 2: Pinout TablesRTable 2-4: FF676 Package — LX15 and LX25 Devices (Continued)Bank Pin Description Pin NumberNo Connects inLX15 Devices9 IO_L24P_CC_LC_9 U22 NC9 IO_L24N_CC_LC_9 T22 NC9 IO_L1P_9 J21 NC9 IO_L1N_9 K21 NC9 IO_L2P_9 H22 NC9 IO_L2N_9 H23 NC9 IO_L3P_9 G24 NC9 IO_L3N_9 G25 NC9 IO_L4P_9 M20 NC9 IO_L4N_VREF_9 M21 NC9 IO_L5P_9 J23 NC9 IO_L5N_9 K22 NC9 IO_L6P_9 J24 NC9 IO_L6N_9 H24 NC9 IO_L7P_9 K23 NC9 IO_L7N_9 L23 NC9 IO_L8P_CC_LC_9 J25 NC9 IO_L8N_CC_LC_9 J26 NC9 IO_L9P_CC_LC_9 G26 NC9 IO_L9N_CC_LC_9 H26 NC9 IO_L10P_9 M22 NC9 IO_L10N_9 N21 NC9 IO_L11P_9 K25 NC9 IO_L11N_9 K26 NC9 IO_L12P_9 L24 NC9 IO_L12N_VREF_9 M24 NC9 IO_L13P_9 N22 NC9 IO_L13N_9 N23 NC9 IO_L14P_9 M26 NC9 IO_L14N_9 N26 NC9 IO_L15P_9 L26 NC9 IO_L15N_9 M25 NC9 IO_L16P_9 P20 NC9 IO_L16N_9 P21 NC9 IO_L25P_CC_LC_9 U24 NC9 IO_L25N_CC_LC_9 U25 NC9 IO_L26P_9 V26 NC80 www.xilinx.com Virtex-4 FPGA Packaging and Pinout SpecificationUG075 (v3.3) September 19, 2008

RFF676 Flip-Chip Fine-Pitch BGA PackageTable 2-4: FF676 Package — LX15 and LX25 Devices (Continued)Bank Pin Description Pin NumberNo Connects inLX15 Devices9 IO_L26N_9 U26 NC9 IO_L27P_9 W24 NC9 IO_L27N_9 V24 NC9 IO_L28P_9 U21 NC9 IO_L28N_VREF_9 T20 NC9 IO_L29P_9 W25 NC9 IO_L29N_9 W26 NC9 IO_L30P_9 Y25 NC9 IO_L30N_9 Y26 NC9 IO_L31P_9 AB25 NC9 IO_L31N_9 AA25 NC9 IO_L32P_9 AC26 NC9 IO_L32N_9 AB26 NC10 IO_L17P_10 R2 NC10 IO_L17N_10 P3 NC10 IO_L18P_10 N4 NC10 IO_L18N_10 P4 NC10 IO_L19P_10 R1 NC10 IO_L19N_10 P1 NC10 IO_L20P_10 P6 NC10 IO_L20N_VREF_10 P5 NC10 IO_L21P_10 T2 NC10 IO_L21N_10 R3 NC10 IO_L22P_10 U4 NC10 IO_L22N_10 T3 NC10 IO_L23P_VRN_10 T4 NC10 IO_L23N_VRP_10 R5 NC10 IO_L24P_CC_LC_10 U2 NC10 IO_L24N_CC_LC_10 U1 NC10 IO_L1P_10 D1 NC10 IO_L1N_10 E1 NC10 IO_L2P_10 H3 NC10 IO_L2N_10 J3 NC10 IO_L3P_10 G2 NC10 IO_L3N_10 G1 NC10 IO_L4P_10 K6 NCVirtex-4 FPGA Packaging and Pinout Specification www.xilinx.com 81UG075 (v3.3) September 19, 2008

Chapter 2: Pinout TablesRTable 2-4: FF676 Package — LX15 and LX25 Devices (Continued)Bank Pin Description Pin NumberNo Connects inLX15 Devices10 IO_L4N_VREF_10 L7 NC10 IO_L5P_10 H2 NC10 IO_L5N_10 H1 NC10 IO_L6P_10 E2 NC10 IO_L6N_10 F2 NC10 IO_L7P_10 K5 NC10 IO_L7N_10 L5 NC10 IO_L8P_CC_LC_10 K3 NC10 IO_L8N_CC_LC_10 K2 NC10 IO_L9P_CC_LC_10 J1 NC10 IO_L9N_CC_LC_10 K1 NC10 IO_L10P_10 L4 NC10 IO_L10N_10 L3 NC10 IO_L11P_10 M5 NC10 IO_L11N_10 M4 NC10 IO_L12P_10 M7 NC10 IO_L12N_VREF_10 M6 NC10 IO_L13P_10 L2 NC10 IO_L13N_10 M1 NC10 IO_L14P_10 N3 NC10 IO_L14N_10 N2 NC10 IO_L15P_10 M2 NC10 IO_L15N_10 N1 NC10 IO_L16P_10 N7 NC10 IO_L16N_10 N6 NC10 IO_L25P_CC_LC_10 V2 NC10 IO_L25N_CC_LC_10 V1 NC10 IO_L26P_10 Y1 NC10 IO_L26N_10 W1 NC10 IO_L27P_10 U6 NC10 IO_L27N_10 U5 NC10 IO_L28P_10 R7 NC10 IO_L28N_VREF_10 R6 NC10 IO_L29P_10 W3 NC10 IO_L29N_10 V3 NC10 IO_L30P_10 W4 NC10 IO_L30N_10 V4 NC82 www.xilinx.com Virtex-4 FPGA Packaging and Pinout SpecificationUG075 (v3.3) September 19, 2008

RFF676 Flip-Chip Fine-Pitch BGA PackageTable 2-4: FF676 Package — LX15 and LX25 Devices (Continued)Bank Pin Description Pin NumberNo Connects inLX15 Devices10 IO_L31P_10 Y3 NC10 IO_L31N_10 Y2 NC10 IO_L32P_10 V6 NC10 IO_L32N_10 W5 NC0 VCCO_0 (1) T110 VCCO_0 (1) M130 VCCO_0 (1) R140 VCCO_0 (1) L161 VCCO_1 J121 VCCO_1 H152 VCCO_2 V152 VCCO_2 W123 VCCO_3 B133 VCCO_3 E144 VCCO_4 AB134 VCCO_4 AE145 VCCO_5 A165 VCCO_5 D175 VCCO_5 G185 VCCO_5 K195 VCCO_5 C205 VCCO_5 F215 VCCO_5 B235 VCCO_5 E245 VCCO_5 A266 VCCO_6 B36 VCCO_6 E46 VCCO_6 H56 VCCO_6 A66 VCCO_6 D76 VCCO_6 G86 VCCO_6 K96 VCCO_6 C106 VCCO_6 F117 VCCO_7 AA167 VCCO_7 AD17Virtex-4 FPGA Packaging and Pinout Specification www.xilinx.com 83UG075 (v3.3) September 19, 2008

Chapter 2: Pinout TablesRTable 2-4: FF676 Package — LX15 and LX25 Devices (Continued)Bank Pin Description Pin NumberNo Connects inLX15 Devices7 VCCO_7 U187 VCCO_7 Y197 VCCO_7 AC207 VCCO_7 AF217 VCCO_7 W227 VCCO_7 AB237 VCCO_7 AE248 VCCO_8 AF18 VCCO_8 AB38 VCCO_8 AE48 VCCO_8 AA68 VCCO_8 AD78 VCCO_8 U88 VCCO_8 Y98 VCCO_8 AC108 VCCO_8 AF119 VCCO_9 N20 NC9 VCCO_9 T21 NC9 VCCO_9 J22 NC9 VCCO_9 M23 NC9 VCCO_9 R24 NC9 VCCO_9 H25 NC9 VCCO_9 L25 NC9 VCCO_9 V25 NC9 VCCO_9 AA26 NC10 VCCO_10 F1 NC10 VCCO_10 T1 NC10 VCCO_10 J2 NC10 VCCO_10 W2 NC10 VCCO_10 M3 NC10 VCCO_10 R4 NC10 VCCO_10 V5 NC10 VCCO_10 L6 NC10 VCCO_10 P7 NCN/A VREFN_SM (2) AE18 NCN/A VREFP_SM (2) AE17 NC84 www.xilinx.com Virtex-4 FPGA Packaging and Pinout SpecificationUG075 (v3.3) September 19, 2008

RFF676 Flip-Chip Fine-Pitch BGA PackageTable 2-4: FF676 Package — LX15 and LX25 Devices (Continued)Bank Pin Description Pin NumberNo Connects inLX15 DevicesN/A AVDD_SM (3) AE16 NCN/A VN_SM (2) AF18 NCN/A VP_SM (2) AF17 NCN/A AVSS_SM (2) AF16 NCN/A GND A1N/A GND L1N/A GND AA1N/A GND D2N/A GND P2N/A GND AD2N/A GND G3N/A GND U3N/A GND K4N/A GND Y4N/A GND C5N/A GND N5N/A GND AC5N/A GND F6N/A GND T6N/A GND AF6N/A GND J7N/A GND W7N/A GND B8N/A GND M8N/A GND P8N/A GND AB8N/A GND E9N/A GND N9N/A GND R9N/A GND AE9N/A GND H10N/A GND M10N/A GND P10N/A GND V10N/A GND A11N/A GND L11Virtex-4 FPGA Packaging and Pinout Specification www.xilinx.com 85UG075 (v3.3) September 19, 2008

Chapter 2: Pinout TablesRTable 2-4: FF676 Package — LX15 and LX25 Devices (Continued)Bank Pin Description Pin NumberN/A GND N11N/A GND AA11N/A GND D12N/A GND P12N/A GND T12N/A GND AD12N/A GND G13N/A GND N13N/A GND U13N/A GND K14N/A GND Y14N/A GND C15N/A GND N15N/A GND AC15N/A GND F16N/A GND P16N/A GND T16N/A GND J17N/A GND N17N/A GND R17N/A GND W17N/A GND B18N/A GND M18N/A GND P18N/A GND AB18N/A GND E19N/A GND N19N/A GND R19N/A GND AE19N/A GND H20N/A GND V20N/A GND A21N/A GND L21N/A GND AA21N/A GND D22N/A GND P22N/A GND AD22No Connects inLX15 Devices86 www.xilinx.com Virtex-4 FPGA Packaging and Pinout SpecificationUG075 (v3.3) September 19, 2008

RFF676 Flip-Chip Fine-Pitch BGA PackageTable 2-4: FF676 Package — LX15 and LX25 Devices (Continued)Bank Pin Description Pin NumberN/A GND G23N/A GND U23N/A GND K24N/A GND Y24N/A GND C25N/A GND N25N/A GND AC25N/A GND F26N/A GND T26N/A GND AF26No Connects inLX15 DevicesN/A VCCAUX J4N/A VCCAUX T5N/A VCCAUX W6N/A VCCAUX H7N/A VCCAUX AA8N/A VCCAUX P9N/A VCCAUX G12N/A VCCAUX N12N/A VCCAUX P15N/A VCCAUX N18N/A VCCAUX F19N/A VCCAUX AF19N/A VCCAUX W20N/A VCCAUX H21N/A VCCAUX L22N/A VCCAUX V23N/A VCCINT K7N/A VCCINT T7N/A VCCINT L8N/A VCCINT N8N/A VCCINT R8N/A VCCINT W8N/A VCCINT F9N/A VCCINT M9N/A VCCINT T9N/A VCCINT V9Virtex-4 FPGA Packaging and Pinout Specification www.xilinx.com 87UG075 (v3.3) September 19, 2008

Chapter 2: Pinout TablesRTable 2-4: FF676 Package — LX15 and LX25 Devices (Continued)Bank Pin Description Pin NumberNo Connects inLX15 DevicesN/A VCCINT G10N/A VCCINT J10N/A VCCINT L10N/A VCCINT N10N/A VCCINT R10N/A VCCINT M11N/A VCCINT P11N/A VCCINT AB11N/A VCCINT L12N/A VCCINT R12N/A VCCINT P13N/A VCCINT T13N/A VCCINT L14N/A VCCINT N14N/A VCCINT M15N/A VCCINT T15N/A VCCINT Y15N/A VCCINT E16N/A VCCINT N16N/A VCCINT R16N/A VCCINT M17N/A VCCINT P17N/A VCCINT T17N/A VCCINT J18N/A VCCINT L18N/A VCCINT R18N/A VCCINT H19N/A VCCINT M19N/A VCCINT P19N/A VCCINT L20N/A VCCINT U20Notes:1. This voltage is also referred to as V CC_CONFIG in the Virtex-4 Configuration Guide.2. For LX25 devices, connect this reserved pin to GND.3. For LX25 devices, connect this reserved pin to 2.5V (sharing the same PCB supply distribution asV CCAUX is acceptable).88 www.xilinx.com Virtex-4 FPGA Packaging and Pinout SpecificationUG075 (v3.3) September 19, 2008

RFF1148 Flip-Chip Fine-Pitch BGA PackageFF1148 Flip-Chip Fine-Pitch BGA PackageAs shown in Table 2-5, the following Virtex-4 LX and SX devices are available in the FF1148flip-chip fine-pitch BGA package:• XC4VLX40• XC4VLX60• XC4VLX80• XC4VLX100• XC4VLX160• XC4VSX55Pinouts in the following devices are identical:• LX40, LX60, and SX55• LX80, LX100, and LX160The “No Connect” column in Table 2-5 shows pins that are not available in LX40, LX60,and SX55 devices.To be assured of having the very latest Virtex-4 FPGA pinout information, visitwww.xilinx.com and check for any updates to this document. ASCII package pinout filesare also available for download from the Xilinx website.Table 2-5: FF1148 Package — LX40, LX60, LX80, LX100, LX160, and SX55 DevicesBankPin DescriptionPinNumber0 HSWAPEN_0 T180 CCLK_0 R170 D_IN_0 T160 PROG_B_0 U220 INIT_B_0 U210 CS_B_0 U170 DONE_0 U150 RDWR_B_0 U130 VBATT_0 V220 M2_0 V200 PWRDWN_B_0 W210 TMS_0 V130 M0_0 W200 TDO_0 V180 TCK_0 V140 M1_0 W19No Connects in LX40,LX60, and SX55 DevicesVirtex-4 FPGA Packaging and Pinout Specification www.xilinx.com 89UG075 (v3.3) September 19, 2008

Chapter 2: Pinout TablesRTable 2-5: FF1148 Package — LX40, LX60, LX80, LX100, LX160, and SX55 Devices(Continued)BankPin DescriptionPinNumber0 DOUT_BUSY_0 Y180 TDI_0 W170 TDN_0 F150 TDP_0 D15No Connects in LX40,LX60, and SX55 Devices1 IO_L1P_D31_LC_1 N191 IO_L1N_D30_LC_1 N181 IO_L2P_D29_LC_1 L151 IO_L2N_D28_LC_1 L141 IO_L3P_D27_LC_1 E211 IO_L3N_D26_LC_1 D211 IO_L4P_D25_LC_1 J141 IO_L4N_D24_VREF_LC_1 K141 IO_L5P_D23_LC_1 N201 IO_L5N_D22_LC_1 M201 IO_L6P_D21_LC_1 H141 IO_L6N_D20_LC_1 H131 IO_L7P_D19_LC_1 H221 IO_L7N_D18_LC_1 J211 IO_L8P_D17_CC_LC_1 F131 IO_L8N_D16_CC_LC_1 G131 IO_L9P_GC_LC_1 M181 IO_L9N_GC_LC_1 L181 IO_L10P_GC_LC_1 M171 IO_L10N_GC_LC_1 N171 IO_L11P_GC_LC_1 E191 IO_L11N_GC_LC_1 D191 IO_L12P_GC_LC_1 C171 IO_L12N_GC_VREF_LC_1 D171 IO_L13P_GC_LC_1 C191 IO_L13N_GC_LC_1 C181 IO_L14P_GC_LC_1 D161 IO_L14N_GC_LC_1 C151 IO_L15P_GC_LC_1 D201 IO_L15N_GC_LC_1 C2090 www.xilinx.com Virtex-4 FPGA Packaging and Pinout SpecificationUG075 (v3.3) September 19, 2008

RFF1148 Flip-Chip Fine-Pitch BGA PackageTable 2-5: FF1148 Package — LX40, LX60, LX80, LX100, LX160, and SX55 Devices(Continued)BankPin DescriptionPinNumber1 IO_L16P_GC_CC_LC_1 M161 IO_L16N_GC_CC_LC_1 N151 IO_L17P_CC_LC_1 B201 IO_L17N_CC_LC_1 A201 IO_L18P_VRN_LC_1 K161 IO_L18N_VRP_LC_1 L161 IO_L19P_LC_1 J201 IO_L19N_LC_1 L191 IO_L20P_LC_1 H151 IO_L20N_VREF_LC_1 J151 IO_L21P_LC_1 G211 IO_L21N_LC_1 H201 IO_L22P_LC_1 G151 IO_L22N_LC_1 F141 IO_L23P_LC_1 F211 IO_L23N_LC_1 F201 IO_L24P_LC_1 A151 IO_L24N_LC_1 B15No Connects in LX40,LX60, and SX55 Devices2 IO_L1P_D15_CC_LC_2 AJ222 IO_L1N_D14_CC_LC_2 AJ212 IO_L2P_D13_LC_2 AC152 IO_L2N_D12_LC_2 AB152 IO_L3P_D11_LC_2 AG222 IO_L3N_D10_LC_2 AH222 IO_L4P_D9_LC_2 AL142 IO_L4N_D8_VREF_LC_2 AK142 IO_L5P_D7_LC_2 AG212 IO_L5N_D6_LC_2 AF202 IO_L6P_D5_LC_2 AF142 IO_L6N_D4_LC_2 AG132 IO_L7P_D3_LC_2 AE212 IO_L7N_D2_LC_2 AF212 IO_L8P_D1_LC_2 AP152 IO_L8N_D0_LC_2 AN15Virtex-4 FPGA Packaging and Pinout Specification www.xilinx.com 91UG075 (v3.3) September 19, 2008

Chapter 2: Pinout TablesRTable 2-5: FF1148 Package — LX40, LX60, LX80, LX100, LX160, and SX55 Devices(Continued)BankPin DescriptionPinNumber2 IO_L9P_GC_CC_LC_2 AC192 IO_L9N_GC_CC_LC_2 AB182 IO_L10P_GC_LC_2 AD162 IO_L10N_GC_LC_2 AF152 IO_L11P_GC_LC_2 AN202 IO_L11N_GC_LC_2 AP202 IO_L12P_GC_LC_2 AD172 IO_L12N_GC_VREF_LC_2 AC172 IO_L13P_GC_LC_2 AM202 IO_L13N_GC_LC_2 AL192 IO_L14P_GC_LC_2 AB172 IO_L14N_GC_LC_2 AB162 IO_L15P_GC_LC_2 AL182 IO_L15N_GC_LC_2 AM182 IO_L16P_GC_LC_2 AM172 IO_L16N_GC_LC_2 AM162 IO_L17P_LC_2 AD212 IO_L17N_LC_2 AD202 IO_L18P_LC_2 AM152 IO_L18N_LC_2 AL152 IO_L19P_LC_2 AJ202 IO_L19N_LC_2 AL202 IO_L20P_LC_2 AJ152 IO_L20N_VREF_LC_2 AJ142 IO_L21P_LC_2 AG202 IO_L21N_LC_2 AH202 IO_L22P_LC_2 AG152 IO_L22N_LC_2 AH142 IO_L23P_VRN_LC_2 AD192 IO_L23N_VRP_LC_2 AE192 IO_L24P_CC_LC_2 AL162 IO_L24N_CC_LC_2 AK16No Connects in LX40,LX60, and SX55 Devices3 IO_L1P_GC_CC_LC_3 F183 IO_L1N_GC_CC_LC_3 G1892 www.xilinx.com Virtex-4 FPGA Packaging and Pinout SpecificationUG075 (v3.3) September 19, 2008

RFF1148 Flip-Chip Fine-Pitch BGA PackageTable 2-5: FF1148 Package — LX40, LX60, LX80, LX100, LX160, and SX55 Devices(Continued)BankPin DescriptionPinNumber3 IO_L2P_GC_VRN_LC_3 H173 IO_L2N_GC_VRP_LC_3 J173 IO_L3P_GC_LC_3 H193 IO_L3N_GC_LC_3 H183 IO_L4P_GC_LC_3 E183 IO_L4N_GC_VREF_LC_3 E173 IO_L5P_GC_LC_3 K183 IO_L5N_GC_LC_3 K173 IO_L6P_GC_LC_3 E163 IO_L6N_GC_LC_3 F163 IO_L7P_GC_LC_3 K193 IO_L7N_GC_LC_3 J193 IO_L8P_GC_LC_3 G173 IO_L8N_GC_LC_3 G16No Connects in LX40,LX60, and SX55 Devices4 IO_L1P_GC_LC_4 AF184 IO_L1N_GC_LC_4 AE184 IO_L2P_GC_LC_4 AG164 IO_L2N_GC_LC_4 AF164 IO_L3P_GC_LC_4 AH194 IO_L3N_GC_LC_4 AH184 IO_L4P_GC_LC_4 AK184 IO_L4N_GC_VREF_LC_4 AK174 IO_L5P_GC_LC_4 AG184 IO_L5N_GC_LC_4 AG174 IO_L6P_GC_LC_4 AE174 IO_L6N_GC_LC_4 AE164 IO_L7P_GC_VRN_LC_4 AJ194 IO_L7N_GC_VRP_LC_4 AK194 IO_L8P_GC_CC_LC_4 AJ174 IO_L8N_GC_CC_LC_4 AH175 IO_L1P_ADC7_5 B235 IO_L1N_ADC7_5 A235 IO_L2P_ADC6_5 A26Virtex-4 FPGA Packaging and Pinout Specification www.xilinx.com 93UG075 (v3.3) September 19, 2008

Chapter 2: Pinout TablesRTable 2-5: FF1148 Package — LX40, LX60, LX80, LX100, LX160, and SX55 Devices(Continued)BankPin DescriptionPinNumber5 IO_L2N_ADC6_5 B265 IO_L3P_ADC5_5 A245 IO_L3N_ADC5_5 A255 IO_L4P_5 G255 IO_L4N_VREF_5 H255 IO_L5P_ADC4_5 C235 IO_L5N_ADC4_5 C245 IO_L6P_ADC3_5 F255 IO_L6N_ADC3_5 F265 IO_L7P_ADC2_5 D245 IO_L7N_ADC2_5 D255 IO_L8P_CC_ADC1_LC_5 B275 IO_L8N_CC_ADC1_LC_5 C275 IO_L17P_5 C225 IO_L17N_5 B225 IO_L18P_5 A305 IO_L18N_5 B305 IO_L19P_5 K245 IO_L19N_5 J245 IO_L20P_5 C295 IO_L20N_VREF_5 C305 IO_L21P_5 B215 IO_L21N_5 A215 IO_L22P_5 E285 IO_L22N_5 F285 IO_L23P_VRN_5 E225 IO_L23N_VRP_5 D225 IO_L24P_CC_LC_5 A315 IO_L24N_CC_LC_5 B315 IO_L9P_CC_LC_5 F235 IO_L9N_CC_LC_5 E235 IO_L10P_5 D265 IO_L10N_5 E265 IO_L11P_5 F245 IO_L11N_5 E245 IO_L12P_5 D27No Connects in LX40,LX60, and SX55 Devices94 www.xilinx.com Virtex-4 FPGA Packaging and Pinout SpecificationUG075 (v3.3) September 19, 2008

RFF1148 Flip-Chip Fine-Pitch BGA PackageTable 2-5: FF1148 Package — LX40, LX60, LX80, LX100, LX160, and SX55 Devices(Continued)BankPin DescriptionPinNumber5 IO_L12N_VREF_5 E275 IO_L13P_5 G235 IO_L13N_5 H245 IO_L14P_5 A285 IO_L14N_5 A295 IO_L15P_5 B255 IO_L15N_5 C255 IO_L16P_5 J255 IO_L16N_5 K265 IO_L25P_CC_LC_5 B285 IO_L25N_CC_LC_5 C285 IO_L26P_5 D305 IO_L26N_5 D315 IO_L27P_5 G275 IO_L27N_5 G285 IO_L28P_5 F295 IO_L28N_VREF_5 F305 IO_L29P_5 D295 IO_L29N_5 E295 IO_L30P_5 L255 IO_L30N_5 L265 IO_L31P_5 B325 IO_L31N_5 B335 IO_L32P_5 E315 IO_L32N_5 F31No Connects in LX40,LX60, and SX55 Devices6 IO_L1P_6 D126 IO_L1N_6 C126 IO_L2P_6 B106 IO_L2N_6 C106 IO_L3P_6 A116 IO_L3N_6 B116 IO_L4P_6 C96 IO_L4N_VREF_6 C86 IO_L5P_6 G12Virtex-4 FPGA Packaging and Pinout Specification www.xilinx.com 95UG075 (v3.3) September 19, 2008

Chapter 2: Pinout TablesRTable 2-5: FF1148 Package — LX40, LX60, LX80, LX100, LX160, and SX55 Devices(Continued)BankPin DescriptionPinNumber6 IO_L5N_6 G116 IO_L6P_6 F106 IO_L6N_6 G106 IO_L7P_6 D116 IO_L7N_6 D106 IO_L8P_CC_LC_6 H106 IO_L8N_CC_LC_6 H96 IO_L17P_6 A146 IO_L17N_6 A136 IO_L18P_6 D76 IO_L18N_6 D66 IO_L19P_6 D96 IO_L19N_6 E96 IO_L20P_6 A46 IO_L20N_VREF_6 A36 IO_L21P_6 E136 IO_L21N_6 E126 IO_L22P_6 A56 IO_L22N_6 B56 IO_L23P_VRN_6 E86 IO_L23N_VRP_6 E76 IO_L24P_CC_LC_6 J96 IO_L24N_CC_LC_6 K96 IO_L9P_CC_LC_6 B136 IO_L9N_CC_LC_6 B126 IO_L10P_6 A86 IO_L10N_6 B86 IO_L11P_6 E116 IO_L11N_6 F116 IO_L12P_6 A66 IO_L12N_VREF_6 B66 IO_L13P_6 H126 IO_L13N_6 J116 IO_L14P_6 B76 IO_L14N_6 C76 IO_L15P_6 A10No Connects in LX40,LX60, and SX55 Devices96 www.xilinx.com Virtex-4 FPGA Packaging and Pinout SpecificationUG075 (v3.3) September 19, 2008

RFF1148 Flip-Chip Fine-Pitch BGA PackageTable 2-5: FF1148 Package — LX40, LX60, LX80, LX100, LX160, and SX55 Devices(Continued)BankPin DescriptionPinNumber6 IO_L15N_6 A96 IO_L16P_6 F86 IO_L16N_6 G86 IO_L25P_CC_LC_6 C146 IO_L25N_CC_LC_6 C136 IO_L26P_6 E66 IO_L26N_6 F66 IO_L27P_6 C56 IO_L27N_6 D56 IO_L28P_6 G76 IO_L28N_VREF_6 G66 IO_L29P_6 E146 IO_L29N_6 D146 IO_L30P_6 B36 IO_L30N_6 B26 IO_L31P_6 H86 IO_L31N_6 H76 IO_L32P_6 K86 IO_L32N_6 J7No Connects in LX40,LX60, and SX55 Devices7 IO_L25P_CC_SM7_LC_7 AL247 IO_L25N_CC_SM7_LC_7 AL257 IO_L26P_SM6_7 AL267 IO_L26N_SM6_7 AK267 IO_L27P_SM5_7 AN227 IO_L27N_SM5_7 AN237 IO_L28P_7 AJ257 IO_L28N_VREF_7 AH257 IO_L29P_SM4_7 AP247 IO_L29N_SM4_7 AN247 IO_L30P_SM3_7 AM267 IO_L30N_SM3_7 AM277 IO_L31P_SM2_7 AL237 IO_L31N_SM2_7 AM237 IO_L32P_SM1_7 AN25Virtex-4 FPGA Packaging and Pinout Specification www.xilinx.com 97UG075 (v3.3) September 19, 2008

Chapter 2: Pinout TablesRTable 2-5: FF1148 Package — LX40, LX60, LX80, LX100, LX160, and SX55 Devices(Continued)BankPin DescriptionPinNumber7 IO_L32N_SM1_7 AM257 IO_L17P_7 AP217 IO_L17N_7 AP227 IO_L18P_7 AP297 IO_L18N_7 AN297 IO_L19P_7 AK247 IO_L19N_7 AJ247 IO_L20P_7 AK277 IO_L20N_VREF_7 AK287 IO_L21P_7 AG237 IO_L21N_7 AF247 IO_L22P_7 AG257 IO_L22N_7 AG267 IO_L23P_VRN_7 AH237 IO_L23N_VRP_7 AH247 IO_L24P_CC_LC_7 AN287 IO_L24N_CC_LC_7 AM287 IO_L1P_7 AK297 IO_L1N_7 AJ297 IO_L2P_7 AF287 IO_L2N_7 AE277 IO_L3P_7 AF267 IO_L3N_7 AE267 IO_L4P_7 AN327 IO_L4N_VREF_7 AN337 IO_L5P_7 AK217 IO_L5N_7 AL217 IO_L6P_7 AH287 IO_L6N_7 AH297 IO_L7P_7 AP307 IO_L7N_7 AN307 IO_L8P_CC_LC_7 AG277 IO_L8N_CC_LC_7 AG287 IO_L9P_CC_LC_7 AM217 IO_L9N_CC_LC_7 AM227 IO_L10P_7 AM30No Connects in LX40,LX60, and SX55 Devices98 www.xilinx.com Virtex-4 FPGA Packaging and Pinout SpecificationUG075 (v3.3) September 19, 2008

RFF1148 Flip-Chip Fine-Pitch BGA PackageTable 2-5: FF1148 Package — LX40, LX60, LX80, LX100, LX160, and SX55 Devices(Continued)BankPin DescriptionPinNumber7 IO_L10N_7 AL307 IO_L11P_7 AP277 IO_L11N_7 AN277 IO_L12P_7 AP317 IO_L12N_VREF_7 AP327 IO_L13P_7 AK227 IO_L13N_7 AK237 IO_L14P_7 AL287 IO_L14N_7 AL297 IO_L15P_7 AP257 IO_L15N_7 AP267 IO_L16P_7 AJ277 IO_L16N_7 AH27No Connects in LX40,LX60, and SX55 Devices8 IO_L25P_CC_LC_8 AL118 IO_L25N_CC_LC_8 AL108 IO_L26P_8 AE118 IO_L26N_8 AF118 IO_L27P_8 AM128 IO_L27N_8 AM118 IO_L28P_8 AL98 IO_L28N_VREF_8 AK98 IO_L29P_8 AP118 IO_L29N_8 AP108 IO_L30P_8 AH108 IO_L30N_8 AG108 IO_L31P_8 AN128 IO_L31N_8 AP128 IO_L32P_8 AP98 IO_L32N_8 AN98 IO_L17P_8 AH128 IO_L17N_8 AG118 IO_L18P_8 AN78 IO_L18N_8 AM78 IO_L19P_8 AN10Virtex-4 FPGA Packaging and Pinout Specification www.xilinx.com 99UG075 (v3.3) September 19, 2008

Chapter 2: Pinout TablesRTable 2-5: FF1148 Package — LX40, LX60, LX80, LX100, LX160, and SX55 Devices(Continued)BankPin DescriptionPinNumber8 IO_L19N_8 AM108 IO_L20P_8 AF108 IO_L20N_VREF_8 AE98 IO_L21P_8 AJ128 IO_L21N_8 AK128 IO_L22P_8 AN88 IO_L22N_8 AM88 IO_L23P_VRN_8 AJ118 IO_L23N_VRP_8 AK118 IO_L24P_CC_LC_8 AP78 IO_L24N_CC_LC_8 AP68 IO_L1P_8 AL58 IO_L1N_8 AL48 IO_L2P_8 AK48 IO_L2N_8 AJ48 IO_L3P_8 AP48 IO_L3N_8 AN48 IO_L4P_8 AD108 IO_L4N_VREF_8 AD98 IO_L5P_8 AN148 IO_L5N_8 AP148 IO_L6P_8 AJ68 IO_L6N_8 AJ58 IO_L7P_8 AK78 IO_L7N_8 AJ78 IO_L8P_CC_LC_8 AN38 IO_L8N_CC_LC_8 AN28 IO_L9P_CC_LC_8 AK138 IO_L9N_CC_LC_8 AL138 IO_L10P_8 AL68 IO_L10N_8 AK68 IO_L11P_8 AL88 IO_L11N_8 AK88 IO_L12P_8 AH88 IO_L12N_VREF_8 AH78 IO_L13P_8 AM13No Connects in LX40,LX60, and SX55 Devices100 www.xilinx.com Virtex-4 FPGA Packaging and Pinout SpecificationUG075 (v3.3) September 19, 2008

RFF1148 Flip-Chip Fine-Pitch BGA PackageTable 2-5: FF1148 Package — LX40, LX60, LX80, LX100, LX160, and SX55 Devices(Continued)BankPin DescriptionPinNumber8 IO_L13N_8 AN138 IO_L14P_8 AM68 IO_L14N_8 AM58 IO_L15P_8 AJ108 IO_L15N_8 AJ98 IO_L16P_8 AP58 IO_L16N_8 AN5No Connects in LX40,LX60, and SX55 Devices9 IO_L17P_9 P209 IO_L17N_9 R199 IO_L18P_9 L289 IO_L18N_9 L299 IO_L19P_9 P249 IO_L19N_9 R249 IO_L20P_9 H329 IO_L20N_VREF_9 J329 IO_L21P_9 M279 IO_L21N_9 M289 IO_L22P_9 H339 IO_L22N_9 H349 IO_L23P_VRN_9 J319 IO_L23N_VRP_9 K319 IO_L24P_CC_LC_9 L309 IO_L24N_CC_LC_9 L319 IO_L1P_9 H279 IO_L1N_9 H289 IO_L2P_9 C329 IO_L2N_9 D329 IO_L3P_9 J279 IO_L3N_9 K279 IO_L4P_9 M259 IO_L4N_VREF_9 M269 IO_L5P_9 N229 IO_L5N_9 N239 IO_L6P_9 H29Virtex-4 FPGA Packaging and Pinout Specification www.xilinx.com 101UG075 (v3.3) September 19, 2008

Chapter 2: Pinout TablesRTable 2-5: FF1148 Package — LX40, LX60, LX80, LX100, LX160, and SX55 Devices(Continued)BankPin DescriptionPinNumber9 IO_L6N_9 H309 IO_L7P_9 C339 IO_L7N_9 C349 IO_L8P_CC_LC_9 D349 IO_L8N_CC_LC_9 E349 IO_L9P_CC_LC_9 G309 IO_L9N_CC_LC_9 G319 IO_L10P_9 J299 IO_L10N_9 J309 IO_L11P_9 E329 IO_L11N_9 E339 IO_L12P_9 N259 IO_L12N_VREF_9 P269 IO_L13P_9 P229 IO_L13N_9 R219 IO_L14P_9 F339 IO_L14N_9 F349 IO_L15P_9 K289 IO_L15N_9 K299 IO_L16P_9 G329 IO_L16N_9 G339 IO_L25P_CC_LC_9 R229 IO_L25N_CC_LC_9 R239 IO_L26P_9 K329 IO_L26N_9 K339 IO_L27P_9 N279 IO_L27N_9 P279 IO_L28P_9 M309 IO_L28N_VREF_9 M319 IO_L29P_9 J349 IO_L29N_9 K349 IO_L30P_9 N299 IO_L30N_9 N309 IO_L31P_9 L339 IO_L31N_9 L349 IO_L32P_9 M32No Connects in LX40,LX60, and SX55 Devices102 www.xilinx.com Virtex-4 FPGA Packaging and Pinout SpecificationUG075 (v3.3) September 19, 2008

RFF1148 Flip-Chip Fine-Pitch BGA PackageTable 2-5: FF1148 Package — LX40, LX60, LX80, LX100, LX160, and SX55 Devices(Continued)BankPin DescriptionPinNumber9 IO_L32N_9 M33No Connects in LX40,LX60, and SX55 Devices10 IO_L17P_10 F110 IO_L17N_10 G110 IO_L18P_10 J410 IO_L18N_10 K410 IO_L19P_10 H310 IO_L19N_10 H210 IO_L20P_10 P1010 IO_L20N_VREF_10 P910 IO_L21P_10 M710 IO_L21N_10 N710 IO_L22P_10 L510 IO_L22N_10 L410 IO_L23P_VRN_10 J210 IO_L23N_VRP_10 J110 IO_L24P_CC_LC_10 R1110 IO_L24N_CC_LC_10 T1110 IO_L1P_10 C410 IO_L1N_10 C310 IO_L2P_10 F510 IO_L2N_10 G510 IO_L3P_10 D410 IO_L3N_10 E410 IO_L4P_10 M1010 IO_L4N_VREF_10 L910 IO_L5P_10 N1310 IO_L5N_10 N1210 IO_L6P_10 F410 IO_L6N_10 F310 IO_L7P_10 C210 IO_L7N_10 D210 IO_L8P_CC_LC_10 D110 IO_L8N_CC_LC_10 E110 IO_L9P_CC_LC_10 E3Virtex-4 FPGA Packaging and Pinout Specification www.xilinx.com 103UG075 (v3.3) September 19, 2008

Chapter 2: Pinout TablesRTable 2-5: FF1148 Package — LX40, LX60, LX80, LX100, LX160, and SX55 Devices(Continued)BankPin DescriptionPinNumber10 IO_L9N_CC_LC_10 E210 IO_L10P_10 J610 IO_L10N_10 J510 IO_L11P_10 H510 IO_L11N_10 H410 IO_L12P_10 N1010 IO_L12N_VREF_10 N910 IO_L13P_10 P1210 IO_L13N_10 P1110 IO_L14P_10 G310 IO_L14N_10 G210 IO_L15P_10 L810 IO_L15N_10 M810 IO_L16P_10 K610 IO_L16N_10 L610 IO_L25P_CC_LC_10 K310 IO_L25N_CC_LC_10 L310 IO_L26P_10 K210 IO_L26N_10 K110 IO_L27P_10 M610 IO_L27N_10 M510 IO_L28P_10 M310 IO_L28N_VREF_10 M210 IO_L29P_10 L110 IO_L29N_10 M110 IO_L30P_10 N510 IO_L30N_10 P510 IO_L31P_10 P710 IO_L31N_10 P610 IO_L32P_10 T1010 IO_L32N_10 R9No Connects in LX40,LX60, and SX55 Devices11 IO_L17P_11 AA2311 IO_L17N_11 AA2411 IO_L18P_11 AJ34104 www.xilinx.com Virtex-4 FPGA Packaging and Pinout SpecificationUG075 (v3.3) September 19, 2008

RFF1148 Flip-Chip Fine-Pitch BGA PackageTable 2-5: FF1148 Package — LX40, LX60, LX80, LX100, LX160, and SX55 Devices(Continued)BankPin DescriptionPinNumber11 IO_L18N_11 AH3411 IO_L19P_11 AD2711 IO_L19N_11 AC2711 IO_L20P_11 AB2511 IO_L20N_VREF_11 AB2611 IO_L21P_11 AG3011 IO_L21N_11 AG3111 IO_L22P_11 AH3211 IO_L22N_11 AH3311 IO_L23P_VRN_11 AC2511 IO_L23N_VRP_11 AD2611 IO_L24P_CC_LC_11 AF2911 IO_L24N_CC_LC_11 AF3011 IO_L1P_11 AA2811 IO_L1N_11 AA2911 IO_L2P_11 W2411 IO_L2N_11 Y2411 IO_L3P_11 AB3011 IO_L3N_11 AA3011 IO_L4P_11 W2511 IO_L4N_VREF_11 Y2611 IO_L5P_11 AE3311 IO_L5N_11 AE3411 IO_L6P_11 AC3211 IO_L6N_11 AC3311 IO_L7P_11 AC2911 IO_L7N_11 AC3011 IO_L8P_CC_LC_11 AD3411 IO_L8N_CC_LC_11 AC3411 IO_L9P_CC_LC_11 AA2511 IO_L9N_CC_LC_11 AA2611 IO_L10P_11 AE3211 IO_L10N_11 AD3211 IO_L11P_11 AC2811 IO_L11N_11 AB2811 IO_L12P_11 AD30No Connects in LX40,LX60, and SX55 DevicesVirtex-4 FPGA Packaging and Pinout Specification www.xilinx.com 105UG075 (v3.3) September 19, 2008

Chapter 2: Pinout TablesRTable 2-5: FF1148 Package — LX40, LX60, LX80, LX100, LX160, and SX55 Devices(Continued)BankPin DescriptionPinNumber11 IO_L12N_VREF_11 AD3111 IO_L13P_11 AG3211 IO_L13N_11 AG3311 IO_L14P_11 AF3311 IO_L14N_11 AF3411 IO_L15P_11 AE2911 IO_L15N_11 AD2911 IO_L16P_11 AF3111 IO_L16N_11 AE3111 IO_L25P_CC_LC_11 AK3111 IO_L25N_CC_LC_11 AK3211 IO_L26P_11 AK3311 IO_L26N_11 AK3411 IO_L27P_11 AM3211 IO_L27N_11 AM3311 IO_L28P_11 AJ3111 IO_L28N_VREF_11 AJ3211 IO_L29P_11 AB2211 IO_L29N_11 AB2311 IO_L30P_11 AL3311 IO_L30N_11 AL3411 IO_L31P_11 AM3111 IO_L31N_11 AL3111 IO_L32P_11 AJ3011 IO_L32N_11 AH30No Connects in LX40,LX60, and SX55 Devices12 IO_L17P_12 AC912 IO_L17N_12 AC812 IO_L18P_12 AG312 IO_L18N_12 AF312 IO_L19P_12 AF612 IO_L19N_12 AE612 IO_L20P_12 AF512 IO_L20N_VREF_12 AF412 IO_L21P_12 AL1106 www.xilinx.com Virtex-4 FPGA Packaging and Pinout SpecificationUG075 (v3.3) September 19, 2008

RFF1148 Flip-Chip Fine-Pitch BGA PackageTable 2-5: FF1148 Package — LX40, LX60, LX80, LX100, LX160, and SX55 Devices(Continued)BankPin DescriptionPinNumber12 IO_L21N_12 AK112 IO_L22P_12 AJ212 IO_L22N_12 AJ112 IO_L23P_VRN_12 AG612 IO_L23N_VRP_12 AG512 IO_L24P_CC_LC_12 AE712 IO_L24N_CC_LC_12 AD712 IO_L1P_12 AB612 IO_L1N_12 AB512 IO_L2P_12 AC312 IO_L2N_12 AC212 IO_L3P_12 Y1112 IO_L3N_12 AA1112 IO_L4P_12 AD212 IO_L4N_VREF_12 AD112 IO_L5P_12 Y1412 IO_L5N_12 AA1312 IO_L6P_12 AC512 IO_L6N_12 AC412 IO_L7P_12 AF112 IO_L7N_12 AE112 IO_L8P_CC_LC_12 AA912 IO_L8N_CC_LC_12 AA812 IO_L9P_CC_LC_12 Y1312 IO_L9N_CC_LC_12 Y1212 IO_L10P_12 AE312 IO_L10N_12 AE212 IO_L11P_12 AD612 IO_L11N_12 AD512 IO_L12P_12 AC712 IO_L12N_VREF_12 AB812 IO_L13P_12 Y1612 IO_L13N_12 AA1512 IO_L14P_12 AE412 IO_L14N_12 AD412 IO_L15P_12 AH3No Connects in LX40,LX60, and SX55 DevicesVirtex-4 FPGA Packaging and Pinout Specification www.xilinx.com 107UG075 (v3.3) September 19, 2008

Chapter 2: Pinout TablesRTable 2-5: FF1148 Package — LX40, LX60, LX80, LX100, LX160, and SX55 Devices(Continued)BankPin DescriptionPinNumber12 IO_L15N_12 AH212 IO_L16P_12 AG212 IO_L16N_12 AG112 IO_L25P_CC_LC_12 AC1012 IO_L25N_CC_LC_12 AB1012 IO_L26P_12 AK312 IO_L26N_12 AK212 IO_L27P_12 AF812 IO_L27N_12 AE812 IO_L28P_12 AH512 IO_L28N_VREF_12 AH412 IO_L29P_12 AB1312 IO_L29N_12 AB1212 IO_L30P_12 AM212 IO_L30N_12 AM112 IO_L31P_12 AG812 IO_L31N_12 AG712 IO_L32P_12 AM312 IO_L32N_12 AL3No Connects in LX40,LX60, and SX55 Devices13 IO_L17P_13 V33 NC13 IO_L17N_13 V34 NC13 IO_L18P_13 U32 NC13 IO_L18N_13 U33 NC13 IO_L19P_13 V25 NC13 IO_L19N_13 U25 NC13 IO_L20P_13 V28 NC13 IO_L20N_VREF_13 V29 NC13 IO_L21P_13 V23 NC13 IO_L21N_13 V24 NC13 IO_L22P_13 W32 NC13 IO_L22N_13 V32 NC13 IO_L23P_VRN_13 Y34 NC13 IO_L23N_VRP_13 W34 NC13 IO_L24P_CC_LC_13 W30 NC108 www.xilinx.com Virtex-4 FPGA Packaging and Pinout SpecificationUG075 (v3.3) September 19, 2008

RFF1148 Flip-Chip Fine-Pitch BGA PackageTable 2-5: FF1148 Package — LX40, LX60, LX80, LX100, LX160, and SX55 Devices(Continued)BankPin DescriptionPinNumberNo Connects in LX40,LX60, and SX55 Devices13 IO_L24N_CC_LC_13 V30 NC13 IO_L1P_13 T23 NC13 IO_L1N_13 U23 NC13 IO_L2P_13 R26 NC13 IO_L2N_13 T26 NC13 IO_L3P_13 T24 NC13 IO_L3N_13 T25 NC13 IO_L4P_13 R27 NC13 IO_L4N_VREF_13 R28 NC13 IO_L5P_13 P29 NC13 IO_L5N_13 R29 NC13 IO_L6P_13 N32 NC13 IO_L6N_13 P32 NC13 IO_L7P_13 P30 NC13 IO_L7N_13 P31 NC13 IO_L8P_CC_LC_13 N33 NC13 IO_L8N_CC_LC_13 N34 NC13 IO_L9P_CC_LC_13 P34 NC13 IO_L9N_CC_LC_13 R34 NC13 IO_L10P_13 R31 NC13 IO_L10N_13 T31 NC13 IO_L11P_13 R32 NC13 IO_L11N_13 R33 NC13 IO_L12P_13 T28 NC13 IO_L12N_VREF_13 U28 NC13 IO_L13P_13 T29 NC13 IO_L13N_13 T30 NC13 IO_L14P_13 T33 NC13 IO_L14N_13 T34 NC13 IO_L15P_13 U26 NC13 IO_L15N_13 U27 NC13 IO_L16P_13 U30 NC13 IO_L16N_13 U31 NC13 IO_L25P_CC_LC_13 Y32 NC13 IO_L25N_CC_LC_13 Y33 NC13 IO_L26P_13 W27 NCVirtex-4 FPGA Packaging and Pinout Specification www.xilinx.com 109UG075 (v3.3) September 19, 2008

Chapter 2: Pinout TablesRTable 2-5: FF1148 Package — LX40, LX60, LX80, LX100, LX160, and SX55 Devices(Continued)BankPin DescriptionPinNumberNo Connects in LX40,LX60, and SX55 Devices13 IO_L26N_13 V27 NC13 IO_L27P_13 Y29 NC13 IO_L27N_13 W29 NC13 IO_L28P_13 Y31 NC13 IO_L28N_VREF_13 W31 NC13 IO_L29P_13 AB32 NC13 IO_L29N_13 AB33 NC13 IO_L30P_13 AA33 NC13 IO_L30N_13 AA34 NC13 IO_L31P_13 AB31 NC13 IO_L31N_13 AA31 NC13 IO_L32P_13 Y27 NC13 IO_L32N_13 Y28 NC14 IO_L17P_14 V9 NC14 IO_L17N_14 V8 NC14 IO_L18P_14 V5 NC14 IO_L18N_14 V4 NC14 IO_L19P_14 W6 NC14 IO_L19N_14 W5 NC14 IO_L20P_14 W2 NC14 IO_L20N_VREF_14 W1 NC14 IO_L21P_14 V12 NC14 IO_L21N_14 W12 NC14 IO_L22P_14 W7 NC14 IO_L22N_14 V7 NC14 IO_L23P_VRN_14 Y4 NC14 IO_L23N_VRP_14 W4 NC14 IO_L24P_CC_LC_14 Y3 NC14 IO_L24N_CC_LC_14 Y2 NC14 IO_L1P_14 N4 NC14 IO_L1N_14 P4 NC14 IO_L2P_14 N3 NC14 IO_L2N_14 N2 NC14 IO_L3P_14 R8 NC110 www.xilinx.com Virtex-4 FPGA Packaging and Pinout SpecificationUG075 (v3.3) September 19, 2008

RFF1148 Flip-Chip Fine-Pitch BGA PackageTable 2-5: FF1148 Package — LX40, LX60, LX80, LX100, LX160, and SX55 Devices(Continued)BankPin DescriptionPinNumberNo Connects in LX40,LX60, and SX55 Devices14 IO_L3N_14 T8 NC14 IO_L4P_14 R7 NC14 IO_L4N_VREF_14 R6 NC14 IO_L5P_14 P2 NC14 IO_L5N_14 P1 NC14 IO_L6P_14 R4 NC14 IO_L6N_14 T4 NC14 IO_L7P_14 R3 NC14 IO_L7N_14 R2 NC14 IO_L8P_CC_LC_14 R1 NC14 IO_L8N_CC_LC_14 T1 NC14 IO_L9P_CC_LC_14 T6 NC14 IO_L9N_CC_LC_14 T5 NC14 IO_L10P_14 T3 NC14 IO_L10N_14 U3 NC14 IO_L11P_14 U8 NC14 IO_L11N_14 U7 NC14 IO_L12P_14 U2 NC14 IO_L12N_VREF_14 U1 NC14 IO_L13P_14 U12 NC14 IO_L13N_14 U11 NC14 IO_L14P_14 U10 NC14 IO_L14N_14 V10 NC14 IO_L15P_14 U6 NC14 IO_L15N_14 U5 NC14 IO_L16P_14 V3 NC14 IO_L16N_14 V2 NC14 IO_L25P_CC_LC_14 AA5 NC14 IO_L25N_CC_LC_14 AA4 NC14 IO_L26P_14 AA1 NC14 IO_L26N_14 Y1 NC14 IO_L27P_14 AB3 NC14 IO_L27N_14 AA3 NC14 IO_L28P_14 AB2 NC14 IO_L28N_VREF_14 AB1 NC14 IO_L29P_14 AA6 NCVirtex-4 FPGA Packaging and Pinout Specification www.xilinx.com 111UG075 (v3.3) September 19, 2008

Chapter 2: Pinout TablesRTable 2-5: FF1148 Package — LX40, LX60, LX80, LX100, LX160, and SX55 Devices(Continued)BankPin DescriptionPinNumberNo Connects in LX40,LX60, and SX55 Devices14 IO_L29N_14 Y6 NC14 IO_L30P_14 Y8 NC14 IO_L30N_14 Y7 NC14 IO_L31P_14 Y9 NC14 IO_L31N_14 W9 NC14 IO_L32P_14 W11 NC14 IO_L32N_14 W10 NC0 VCCO_0 (1) U140 VCCO_0 (1) T170 VCCO_0 (1) W180 VCCO_0 (1) V211 VCCO_1 G141 VCCO_1 K151 VCCO_1 C161 VCCO_1 N161 VCCO_1 B191 VCCO_1 M191 VCCO_1 E201 VCCO_1 H212 VCCO_2 AG142 VCCO_2 AK152 VCCO_2 AC162 VCCO_2 AN162 VCCO_2 AB192 VCCO_2 AM192 VCCO_2 AE202 VCCO_2 AH213 VCCO_3 F173 VCCO_3 J184 VCCO_4 AF174 VCCO_4 AJ185 VCCO_5 A225 VCCO_5 D235 VCCO_5 G24112 www.xilinx.com Virtex-4 FPGA Packaging and Pinout SpecificationUG075 (v3.3) September 19, 2008

RFF1148 Flip-Chip Fine-Pitch BGA PackageTable 2-5: FF1148 Package — LX40, LX60, LX80, LX100, LX160, and SX55 Devices(Continued)BankPin DescriptionPinNumber5 VCCO_5 K255 VCCO_5 C265 VCCO_5 F275 VCCO_5 B295 VCCO_5 E305 VCCO_5 A326 VCCO_6 A26 VCCO_6 C66 VCCO_6 F76 VCCO_6 J86 VCCO_6 B96 VCCO_6 E106 VCCO_6 H116 VCCO_6 A126 VCCO_6 D137 VCCO_7 AL227 VCCO_7 AP237 VCCO_7 AG247 VCCO_7 AK257 VCCO_7 AN267 VCCO_7 AF277 VCCO_7 AJ287 VCCO_7 AM297 VCCO_7 AP338 VCCO_8 AP38 VCCO_8 AK58 VCCO_8 AN68 VCCO_8 AJ88 VCCO_8 AM98 VCCO_8 AE108 VCCO_8 AH118 VCCO_8 AL128 VCCO_8 AP139 VCCO_9 R209 VCCO_9 P239 VCCO_9 N26No Connects in LX40,LX60, and SX55 DevicesVirtex-4 FPGA Packaging and Pinout Specification www.xilinx.com 113UG075 (v3.3) September 19, 2008

Chapter 2: Pinout TablesRTable 2-5: FF1148 Package — LX40, LX60, LX80, LX100, LX160, and SX55 Devices(Continued)BankPin DescriptionPinNumberNo Connects in LX40,LX60, and SX55 Devices9 VCCO_9 J289 VCCO_9 M299 VCCO_9 H319 VCCO_9 L329 VCCO_9 D339 VCCO_9 G3410 VCCO_10 H110 VCCO_10 L210 VCCO_10 D310 VCCO_10 G410 VCCO_10 K510 VCCO_10 N610 VCCO_10 M910 VCCO_10 R1010 VCCO_10 P1311 VCCO_11 AA2211 VCCO_11 Y2511 VCCO_11 AC2611 VCCO_11 AB2911 VCCO_11 AE3011 VCCO_11 AH3111 VCCO_11 AL3211 VCCO_11 AD3311 VCCO_11 AG3412 VCCO_12 AH112 VCCO_12 AL212 VCCO_12 AD312 VCCO_12 AG412 VCCO_12 AC612 VCCO_12 AF712 VCCO_12 AB912 VCCO_12 AA1212 VCCO_12 Y1513 VCCO_13 U24 NC13 VCCO_13 T27 NC13 VCCO_13 W28 NC114 www.xilinx.com Virtex-4 FPGA Packaging and Pinout SpecificationUG075 (v3.3) September 19, 2008

RFF1148 Flip-Chip Fine-Pitch BGA PackageTable 2-5: FF1148 Package — LX40, LX60, LX80, LX100, LX160, and SX55 Devices(Continued)BankPin DescriptionPinNumberNo Connects in LX40,LX60, and SX55 Devices13 VCCO_13 R30 NC13 VCCO_13 V31 NC13 VCCO_13 AA32 NC13 VCCO_13 P33 NC13 VCCO_13 U34 NC14 VCCO_14 V1 NC14 VCCO_14 AA2 NC14 VCCO_14 P3 NC14 VCCO_14 U4 NC14 VCCO_14 Y5 NC14 VCCO_14 T7 NC14 VCCO_14 W8 NC14 VCCO_14 V11 NCN/A VREFN_SM (2) AN17N/A VREFP_SM (2) AN18N/A AVDD_SM (3) AP19N/A VN_SM (2) AP17N/A VP_SM (2) AP18N/A AVSS_SM (2) AN19N/A VREFN_ADC (2) B17 NCN/A VREFP_ADC (2) B18 NCN/A AVDD_ADC (3) B16 NCN/A VN_ADC (2) A17 NCN/A VP_ADC (2) A18 NCN/A AVSS_ADC (2) A16 NCN/A GND B1N/A GND C1N/A GND N1N/A GND AC1N/A GND AN1N/A GND F2N/A GND T2Virtex-4 FPGA Packaging and Pinout Specification www.xilinx.com 115UG075 (v3.3) September 19, 2008

Chapter 2: Pinout TablesRTable 2-5: FF1148 Package — LX40, LX60, LX80, LX100, LX160, and SX55 Devices(Continued)BankPin DescriptionPinNumberN/A GND AF2N/A GND AP2N/A GND J3N/A GND W3N/A GND AJ3N/A GND B4N/A GND M4N/A GND AB4N/A GND AM4N/A GND E5N/A GND R5N/A GND AE5N/A GND H6N/A GND V6N/A GND AH6N/A GND A7N/A GND L7N/A GND AA7N/A GND AL7N/A GND D8N/A GND P8N/A GND AD8N/A GND AP8N/A GND G9N/A GND U9N/A GND AG9N/A GND K10N/A GND Y10N/A GND AK10N/A GND C11N/A GND L11N/A GND N11N/A GND AC11N/A GND AN11N/A GND F12N/A GND K12No Connects in LX40,LX60, and SX55 Devices116 www.xilinx.com Virtex-4 FPGA Packaging and Pinout SpecificationUG075 (v3.3) September 19, 2008

RFF1148 Flip-Chip Fine-Pitch BGA PackageTable 2-5: FF1148 Package — LX40, LX60, LX80, LX100, LX160, and SX55 Devices(Continued)BankPin DescriptionPinNumberN/A GND M12N/A GND T12N/A GND AD12N/A GND AF12N/A GND J13N/A GND L13N/A GND R13N/A GND W13N/A GND AC13N/A GND AE13N/A GND AJ13N/A GND B14N/A GND M14N/A GND T14N/A GND AB14N/A GND AD14N/A GND AM14N/A GND E15N/A GND R15N/A GND W15N/A GND AE15N/A GND H16N/A GND P16N/A GND V16N/A GND AH16N/A GND AP16N/A GND L17N/A GND AA17N/A GND AL17N/A GND D18N/A GND P18N/A GND AD18N/A GND A19N/A GND G19N/A GND U19N/A GND AA19No Connects in LX40,LX60, and SX55 DevicesVirtex-4 FPGA Packaging and Pinout Specification www.xilinx.com 117UG075 (v3.3) September 19, 2008

Chapter 2: Pinout TablesRTable 2-5: FF1148 Package — LX40, LX60, LX80, LX100, LX160, and SX55 Devices(Continued)BankPin DescriptionPinNumberN/A GND AG19N/A GND K20N/A GND T20N/A GND Y20N/A GND AB20N/A GND AK20N/A GND C21N/A GND L21N/A GND N21N/A GND AC21N/A GND AN21N/A GND F22N/A GND K22N/A GND M22N/A GND T22N/A GND Y22N/A GND AD22N/A GND AF22N/A GND J23N/A GND L23N/A GND W23N/A GND AC23N/A GND AE23N/A GND AJ23N/A GND B24N/A GND M24N/A GND AB24N/A GND AD24N/A GND AM24N/A GND E25N/A GND R25N/A GND AE25N/A GND H26N/A GND V26N/A GND AH26N/A GND A27No Connects in LX40,LX60, and SX55 Devices118 www.xilinx.com Virtex-4 FPGA Packaging and Pinout SpecificationUG075 (v3.3) September 19, 2008

RFF1148 Flip-Chip Fine-Pitch BGA PackageTable 2-5: FF1148 Package — LX40, LX60, LX80, LX100, LX160, and SX55 Devices(Continued)BankPin DescriptionPinNumberN/A GND L27N/A GND AA27N/A GND AL27N/A GND D28N/A GND P28N/A GND AD28N/A GND AP28N/A GND G29N/A GND U29N/A GND AG29N/A GND K30N/A GND Y30N/A GND AK30N/A GND C31N/A GND N31N/A GND AC31N/A GND AN31N/A GND F32N/A GND T32N/A GND AF32N/A GND A33N/A GND J33N/A GND W33N/A GND AJ33N/A GND B34N/A GND M34N/A GND AB34N/A GND AM34N/A GND AN34No Connects in LX40,LX60, and SX55 DevicesN/A VCCAUX N8N/A VCCAUX F9N/A VCCAUX T9N/A VCCAUX AH9N/A VCCAUX J10Virtex-4 FPGA Packaging and Pinout Specification www.xilinx.com 119UG075 (v3.3) September 19, 2008

Chapter 2: Pinout TablesRTable 2-5: FF1148 Package — LX40, LX60, LX80, LX100, LX160, and SX55 Devices(Continued)BankPin DescriptionPinNumberN/A VCCAUX AA10N/A VCCAUX M11N/A VCCAUX AD11N/A VCCAUX AG12N/A VCCAUX U16N/A VCCAUX AJ16N/A VCCAUX Y17N/A VCCAUX R18N/A VCCAUX F19N/A VCCAUX V19N/A VCCAUX H23N/A VCCAUX L24N/A VCCAUX AC24N/A VCCAUX P25N/A VCCAUX AF25N/A VCCAUX G26N/A VCCAUX W26N/A VCCAUX AJ26N/A VCCAUX AB27N/A VCCINT K7N/A VCCINT AB7N/A VCCINT AF9N/A VCCINT L10N/A VCCINT K11N/A VCCINT AB11N/A VCCINT J12N/A VCCINT L12N/A VCCINT R12N/A VCCINT AC12N/A VCCINT AE12N/A VCCINT K13N/A VCCINT M13N/A VCCINT T13N/A VCCINT AD13N/A VCCINT AF13N/A VCCINT AH13No Connects in LX40,LX60, and SX55 Devices120 www.xilinx.com Virtex-4 FPGA Packaging and Pinout SpecificationUG075 (v3.3) September 19, 2008

RFF1148 Flip-Chip Fine-Pitch BGA PackageTable 2-5: FF1148 Package — LX40, LX60, LX80, LX100, LX160, and SX55 Devices(Continued)BankPin DescriptionPinNumberN/A VCCINT N14N/A VCCINT R14N/A VCCINT W14N/A VCCINT AC14N/A VCCINT AE14N/A VCCINT M15N/A VCCINT P15N/A VCCINT T15N/A VCCINT V15N/A VCCINT AD15N/A VCCINT AH15N/A VCCINT J16N/A VCCINT R16N/A VCCINT W16N/A VCCINT AA16N/A VCCINT P17N/A VCCINT V17N/A VCCINT U18N/A VCCINT AA18N/A VCCINT AC18N/A VCCINT P19N/A VCCINT T19N/A VCCINT Y19N/A VCCINT AF19N/A VCCINT G20N/A VCCINT L20N/A VCCINT U20N/A VCCINT AA20N/A VCCINT AC20N/A VCCINT K21N/A VCCINT M21N/A VCCINT T21N/A VCCINT Y21N/A VCCINT AB21N/A VCCINT G22N/A VCCINT J22No Connects in LX40,LX60, and SX55 DevicesVirtex-4 FPGA Packaging and Pinout Specification www.xilinx.com 121UG075 (v3.3) September 19, 2008

Chapter 2: Pinout TablesRTable 2-5: FF1148 Package — LX40, LX60, LX80, LX100, LX160, and SX55 Devices(Continued)BankPin DescriptionPinNumberNo Connects in LX40,LX60, and SX55 DevicesN/A VCCINT L22N/A VCCINT W22N/A VCCINT AC22N/A VCCINT AE22N/A VCCINT K23N/A VCCINT M23N/A VCCINT Y23N/A VCCINT AD23N/A VCCINT AF23N/A VCCINT N24N/A VCCINT AE24N/A VCCINT AD25N/A VCCINT J26N/A VCCINT N28N/A VCCINT AE28Notes:1. This voltage is also referred to as V CC_CONFIG in the Virtex-4 Configuration Guide.2. Connect this reserved pin to GND.3. Connect this reserved pin to 2.5V (sharing the same PCB supply distribution as V CCAUX is acceptable).122 www.xilinx.com Virtex-4 FPGA Packaging and Pinout SpecificationUG075 (v3.3) September 19, 2008

RFF1152 Flip-Chip Fine-Pitch BGA PackageFF1152 Flip-Chip Fine-Pitch BGA PackageAs shown in Table 2-6, Virtex-4 XC4VFX40, XC4VFX60, and XC4VFX100 devices areavailable in the FF1152 flip-chip fine-pitch BGA package.The “No Connect” columns in Table 2-6 show pins that are not available in FX60 and FX40devices.To be assured of having the very latest Virtex-4 FPGA pinout information, visitwww.xilinx.com and check for any updates to this document. ASCII package pinout filesare also available for download from the Xilinx website.Table 2-6: FF1152 Package — FX40, FX60, and FX100 DevicesBankPin DescriptionPinNumber0 HSWAPEN_0 P200 CCLK_0 T180 D_IN_0 R170 PROG_B_0 P210 INIT_B_0 P190 CS_B_0 T160 DONE_0 R190 RDWR_B_0 W150 VBATT_0 R210 M2_0 T200 PWRDWN_B_0 AA160 TMS_0 Y140 M0_0 V180 TDO_0 W170 TCK_0 AA140 M1_0 W190 DOUT_BUSY_0 Y180 TDI_0 AA150 TDN_0 D170 TDP_0 C17No Connects inFX60 DevicesNo Connects inFX40 Devices1 IO_L1P_D31_LC_1 G181 IO_L1N_D30_LC_1 F181 IO_L2P_D29_LC_1 H141 IO_L2N_D28_LC_1 H131 IO_L3P_D27_LC_1 G171 IO_L3N_D26_LC_1 G161 IO_L4P_D25_LC_1 G151 IO_L4N_D24_VREF_LC_1 H15Virtex-4 FPGA Packaging and Pinout Specification www.xilinx.com 123UG075 (v3.3) September 19, 2008

Chapter 2: Pinout TablesRTable 2-6: FF1152 Package — FX40, FX60, and FX100 Devices (Continued)BankPin DescriptionPinNumber1 IO_L5P_D23_LC_1 E181 IO_L5N_D22_LC_1 E171 IO_L6P_D21_LC_1 F151 IO_L6N_D20_LC_1 F141 IO_L7P_D19_LC_1 E161 IO_L7N_D18_LC_1 F161 IO_L8P_D17_CC_LC_1 F131 IO_L8N_D16_CC_LC_1 G13No Connects inFX60 DevicesNo Connects inFX40 Devices2 IO_L1P_D15_CC_LC_2 AH222 IO_L1N_D14_CC_LC_2 AJ222 IO_L2P_D13_LC_2 AK182 IO_L2N_D12_LC_2 AK172 IO_L3P_D11_LC_2 AG222 IO_L3N_D10_LC_2 AG212 IO_L4P_D9_LC_2 AH172 IO_L4N_D8_VREF_LC_2 AJ172 IO_L5P_D7_LC_2 AJ212 IO_L5N_D6_LC_2 AJ202 IO_L6P_D5_LC_2 AJ192 IO_L6N_D4_LC_2 AK192 IO_L7P_D3_LC_2 AG202 IO_L7N_D2_LC_2 AH202 IO_L8P_D1_LC_2 AH192 IO_L8N_D0_LC_2 AH183 IO_L1P_GC_CC_LC_3 H173 IO_L1N_GC_CC_LC_3 J173 IO_L2P_GC_VRN_LC_3 K163 IO_L2N_GC_VRP_LC_3 L163 IO_L3P_GC_LC_3 K183 IO_L3N_GC_LC_3 K173 IO_L4P_GC_LC_3 J163 IO_L4N_GC_VREF_LC_3 J153 IO_L5P_GC_LC_3 K193 IO_L5N_GC_LC_3 J19124 www.xilinx.com Virtex-4 FPGA Packaging and Pinout SpecificationUG075 (v3.3) September 19, 2008

RFF1152 Flip-Chip Fine-Pitch BGA PackageTable 2-6: FF1152 Package — FX40, FX60, and FX100 Devices (Continued)BankPin DescriptionPinNumber3 IO_L6P_GC_LC_3 J143 IO_L6N_GC_LC_3 K143 IO_L7P_GC_LC_3 H193 IO_L7N_GC_LC_3 H183 IO_L8P_GC_LC_3 L153 IO_L8N_GC_LC_3 L14No Connects inFX60 DevicesNo Connects inFX40 Devices4 IO_L1P_GC_LC_4 AD214 IO_L1N_GC_LC_4 AD204 IO_L2P_GC_LC_4 AF164 IO_L2N_GC_LC_4 AE164 IO_L3P_GC_LC_4 AE214 IO_L3N_GC_LC_4 AF214 IO_L4P_GC_LC_4 AE184 IO_L4N_GC_VREF_LC_4 AE174 IO_L5P_GC_LC_4 AF204 IO_L5N_GC_LC_4 AF194 IO_L6P_GC_LC_4 AG174 IO_L6N_GC_LC_4 AG164 IO_L7P_GC_VRN_LC_4 AD194 IO_L7N_GC_VRP_LC_4 AE194 IO_L8P_GC_CC_LC_4 AF184 IO_L8N_GC_CC_LC_4 AG185 IO_L1P_ADC7_5 H245 IO_L1N_ADC7_5 J245 IO_L2P_ADC6_5 E235 IO_L2N_ADC6_5 F235 IO_L3P_ADC5_5 E245 IO_L3N_ADC5_5 F245 IO_L4P_5 G235 IO_L4N_VREF_5 H235 IO_L5P_ADC4_5 C245 IO_L5N_ADC4_5 D245 IO_L6P_ADC3_5 C235 IO_L6N_ADC3_5 C22Virtex-4 FPGA Packaging and Pinout Specification www.xilinx.com 125UG075 (v3.3) September 19, 2008

Chapter 2: Pinout TablesRTable 2-6: FF1152 Package — FX40, FX60, and FX100 Devices (Continued)BankPin DescriptionPinNumber5 IO_L7P_ADC2_5 J255 IO_L7N_ADC2_5 H255 IO_L8P_CC_ADC1_LC_5 G225 IO_L8N_CC_ADC1_LC_5 H225 IO_L17P_5 K265 IO_L17N_5 J265 IO_L18P_5 D215 IO_L18N_5 E215 IO_L19P_5 E275 IO_L19N_5 D275 IO_L20P_5 K235 IO_L20N_VREF_5 L235 IO_L21P_5 C285 IO_L21N_5 C275 IO_L22P_5 H205 IO_L22N_5 J205 IO_L23P_VRN_5 G285 IO_L23N_VRP_5 G275 IO_L24P_CC_LC_5 F205 IO_L24N_CC_LC_5 G205 IO_L9P_CC_LC_5 G255 IO_L9N_CC_LC_5 F255 IO_L10P_5 D225 IO_L10N_5 E225 IO_L11P_5 D255 IO_L11N_5 C255 IO_L12P_5 J225 IO_L12N_VREF_5 K225 IO_L13P_5 G265 IO_L13N_5 F265 IO_L14P_5 J215 IO_L14N_5 K215 IO_L15P_5 E265 IO_L15N_5 D265 IO_L16P_5 F215 IO_L16N_5 G215 IO_L25P_CC_LC_5 F28No Connects inFX60 DevicesNo Connects inFX40 Devices126 www.xilinx.com Virtex-4 FPGA Packaging and Pinout SpecificationUG075 (v3.3) September 19, 2008

RFF1152 Flip-Chip Fine-Pitch BGA PackageTable 2-6: FF1152 Package — FX40, FX60, and FX100 Devices (Continued)BankPin DescriptionPinNumber5 IO_L25N_CC_LC_5 E285 IO_L26P_5 E195 IO_L26N_5 F195 IO_L27P_5 K245 IO_L27N_5 L245 IO_L28P_5 L215 IO_L28N_VREF_5 M225 IO_L29P_5 L265 IO_L29N_5 L255 IO_L30P_5 P225 IO_L30N_5 N225 IO_L31P_5 P245 IO_L31N_5 N245 IO_L32P_5 N235 IO_L32N_5 M23No Connects inFX60 DevicesNo Connects inFX40 Devices6 IO_L1P_6 G106 IO_L1N_6 H106 IO_L2P_6 D106 IO_L2N_6 C106 IO_L3P_6 F106 IO_L3N_6 F96 IO_L4P_6 H96 IO_L4N_VREF_6 J96 IO_L5P_6 F116 IO_L5N_6 E116 IO_L6P_6 D96 IO_L6N_6 E96 IO_L7P_6 D126 IO_L7N_6 D116 IO_L8P_CC_LC_6 C96 IO_L8N_CC_LC_6 C86 IO_L17P_6 J126 IO_L17N_6 H126 IO_L18P_6 E76 IO_L18N_6 E6Virtex-4 FPGA Packaging and Pinout Specification www.xilinx.com 127UG075 (v3.3) September 19, 2008

Chapter 2: Pinout TablesRTable 2-6: FF1152 Package — FX40, FX60, and FX100 Devices (Continued)BankPin DescriptionPinNumber6 IO_L19P_6 E136 IO_L19N_6 E126 IO_L20P_6 K96 IO_L20N_VREF_6 K86 IO_L21P_6 E146 IO_L21N_6 D146 IO_L22P_6 C76 IO_L22N_6 D76 IO_L23P_VRN_6 C156 IO_L23N_VRP_6 C146 IO_L24P_CC_LC_6 F66 IO_L24N_CC_LC_6 G66 IO_L9P_CC_LC_6 C136 IO_L9N_CC_LC_6 C126 IO_L10P_6 E86 IO_L10N_6 F86 IO_L11P_6 J116 IO_L11N_6 J106 IO_L12P_6 G86 IO_L12N_VREF_6 H86 IO_L13P_6 G126 IO_L13N_6 G116 IO_L14P_6 J76 IO_L14N_6 K76 IO_L15P_6 K116 IO_L15N_6 L116 IO_L16P_6 G76 IO_L16N_6 H76 IO_L25P_CC_LC_6 D166 IO_L25N_CC_LC_6 D156 IO_L26P_6 D66 IO_L26N_6 C56 IO_L27P_6 K136 IO_L27N_6 K126 IO_L28P_6 D56 IO_L28N_VREF_6 D46 IO_L29P_6 M13No Connects inFX60 DevicesNo Connects inFX40 Devices128 www.xilinx.com Virtex-4 FPGA Packaging and Pinout SpecificationUG075 (v3.3) September 19, 2008

RFF1152 Flip-Chip Fine-Pitch BGA PackageTable 2-6: FF1152 Package — FX40, FX60, and FX100 Devices (Continued)BankPin DescriptionPinNumber6 IO_L29N_6 L136 IO_L30P_6 E46 IO_L30N_6 E36 IO_L31P_6 M126 IO_L31N_6 M116 IO_L32P_6 C46 IO_L32N_6 C3No Connects inFX60 DevicesNo Connects inFX40 Devices7 IO_L25P_CC_SM7_LC_7 AH277 IO_L25N_CC_SM7_LC_7 AJ277 IO_L26P_SM6_7 AL257 IO_L26N_SM6_7 AM257 IO_L27P_SM5_7 AF267 IO_L27N_SM5_7 AG267 IO_L28P_7 AD247 IO_L28N_VREF_7 AE247 IO_L29P_SM4_7 AG257 IO_L29N_SM4_7 AH257 IO_L30P_SM3_7 AL267 IO_L30N_SM3_7 AM267 IO_L31P_SM2_7 AF257 IO_L31N_SM2_7 AF247 IO_L32P_SM1_7 AJ267 IO_L32N_SM1_7 AJ257 IO_L17P_7 AG287 IO_L17N_7 AG277 IO_L18P_7 AH237 IO_L18N_7 AG237 IO_L19P_7 AE287 IO_L19N_7 AF287 IO_L20P_7 AF237 IO_L20N_VREF_7 AE237 IO_L21P_7 AE277 IO_L21N_7 AE267 IO_L22P_7 AL247 IO_L22N_7 AK24Virtex-4 FPGA Packaging and Pinout Specification www.xilinx.com 129UG075 (v3.3) September 19, 2008

Chapter 2: Pinout TablesRTable 2-6: FF1152 Package — FX40, FX60, and FX100 Devices (Continued)BankPin DescriptionPinNumber7 IO_L23P_VRN_7 AK277 IO_L23N_VRP_7 AK267 IO_L24P_CC_LC_7 AJ247 IO_L24N_CC_LC_7 AH247 IO_L1P_7 AK327 IO_L1N_7 AK317 IO_L2P_7 AL197 IO_L2N_7 AL187 IO_L3P_7 AM327 IO_L3N_7 AM317 IO_L4P_7 AC237 IO_L4N_VREF_7 AC227 IO_L5P_7 AL317 IO_L5N_7 AL307 IO_L6P_7 AM207 IO_L6N_7 AL207 IO_L7P_7 AM307 IO_L7N_7 AL297 IO_L8P_CC_LC_7 AL217 IO_L8N_CC_LC_7 AK217 IO_L9P_CC_LC_7 AJ297 IO_L9N_CC_LC_7 AK297 IO_L10P_7 AM227 IO_L10N_7 AM217 IO_L11P_7 AH297 IO_L11N_7 AH287 IO_L12P_7 AE227 IO_L12N_VREF_7 AD227 IO_L13P_7 AM287 IO_L13N_7 AM277 IO_L14P_7 AM237 IO_L14N_7 AL237 IO_L15P_7 AK287 IO_L15N_7 AL287 IO_L16P_7 AK237 IO_L16N_7 AK22No Connects inFX60 DevicesNo Connects inFX40 Devices130 www.xilinx.com Virtex-4 FPGA Packaging and Pinout SpecificationUG075 (v3.3) September 19, 2008

RFF1152 Flip-Chip Fine-Pitch BGA PackageTable 2-6: FF1152 Package — FX40, FX60, and FX100 Devices (Continued)BankPin DescriptionPinNumberNo Connects inFX60 DevicesNo Connects inFX40 Devices8 IO_L25P_CC_LC_8 AG138 IO_L25N_CC_LC_8 AH138 IO_L26P_8 AJ128 IO_L26N_8 AK128 IO_L27P_8 AF118 IO_L27N_8 AG118 IO_L28P_8 AF98 IO_L28N_VREF_8 AE98 IO_L29P_8 AG128 IO_L29N_8 AH128 IO_L30P_8 AM138 IO_L30N_8 AM128 IO_L31P_8 AK148 IO_L31N_8 AL148 IO_L32P_8 AK138 IO_L32N_8 AL138 IO_L17P_8 AF158 IO_L17N_8 AG158 IO_L18P_8 AH108 IO_L18N_8 AJ108 IO_L19P_8 AJ168 IO_L19N_8 AK168 IO_L20P_8 AF108 IO_L20N_VREF_8 AG108 IO_L21P_8 AH158 IO_L21N_8 AJ158 IO_L22P_8 AL118 IO_L22N_8 AM118 IO_L23P_VRN_8 AH148 IO_L23N_VRP_8 AJ148 IO_L24P_CC_LC_8 AJ118 IO_L24N_CC_LC_8 AK118 IO_L1P_8 AB118 IO_L1N_8 AA118 IO_L2P_8 AK7Virtex-4 FPGA Packaging and Pinout Specification www.xilinx.com 131UG075 (v3.3) September 19, 2008

Chapter 2: Pinout TablesRTable 2-6: FF1152 Package — FX40, FX60, and FX100 Devices (Continued)BankPin DescriptionPinNumber8 IO_L2N_8 AJ78 IO_L3P_8 AB138 IO_L3N_8 AA138 IO_L4P_8 AH88 IO_L4N_VREF_8 AH78 IO_L5P_8 AC128 IO_L5N_8 AB128 IO_L6P_8 AM88 IO_L6N_8 AM78 IO_L7P_8 AD148 IO_L7N_8 AC138 IO_L8P_CC_LC_8 AL88 IO_L8N_CC_LC_8 AK88 IO_L9P_CC_LC_8 AD128 IO_L9N_CC_LC_8 AE128 IO_L10P_8 AL98 IO_L10N_8 AK98 IO_L11P_8 AD118 IO_L11N_8 AE118 IO_L12P_8 AD108 IO_L12N_VREF_8 AD98 IO_L13P_8 AE148 IO_L13N_8 AF148 IO_L14P_8 AJ98 IO_L14N_8 AH98 IO_L15P_8 AE138 IO_L15N_8 AF138 IO_L16P_8 AL108 IO_L16N_8 AM10No Connects inFX60 DevicesNo Connects inFX40 Devices9 IO_L17P_9 L319 IO_L17N_9 L309 IO_L18P_9 J329 IO_L18N_9 H329 IO_L19P_9 N299 IO_L19N_9 N28132 www.xilinx.com Virtex-4 FPGA Packaging and Pinout SpecificationUG075 (v3.3) September 19, 2008

RFF1152 Flip-Chip Fine-Pitch BGA PackageTable 2-6: FF1152 Package — FX40, FX60, and FX100 Devices (Continued)BankPin DescriptionPinNumber9 IO_L20P_9 N279 IO_L20N_VREF_9 M289 IO_L21P_9 N309 IO_L21N_9 M309 IO_L22P_9 M329 IO_L22N_9 M319 IO_L23P_VRN_9 P319 IO_L23N_VRP_9 P309 IO_L24P_CC_LC_9 P279 IO_L24N_CC_LC_9 P269 IO_L1P_9 E319 IO_L1N_9 D319 IO_L2P_9 D299 IO_L2N_9 C299 IO_L3P_9 E329 IO_L3N_9 F319 IO_L4P_9 H289 IO_L4N_VREF_9 H279 IO_L5P_9 G309 IO_L5N_9 F309 IO_L6P_9 D309 IO_L6N_9 C309 IO_L7P_9 G329 IO_L7N_9 G319 IO_L8P_CC_LC_9 F299 IO_L8N_CC_LC_9 E299 IO_L9P_CC_LC_9 K299 IO_L9N_CC_LC_9 J299 IO_L10P_9 D329 IO_L10N_9 C329 IO_L11P_9 J319 IO_L11N_9 J309 IO_L12P_9 K289 IO_L12N_VREF_9 J279 IO_L13P_9 L299 IO_L13N_9 L289 IO_L14P_9 H30No Connects inFX60 DevicesNo Connects inFX40 DevicesVirtex-4 FPGA Packaging and Pinout Specification www.xilinx.com 133UG075 (v3.3) September 19, 2008

Chapter 2: Pinout TablesRTable 2-6: FF1152 Package — FX40, FX60, and FX100 Devices (Continued)BankPin DescriptionPinNumber9 IO_L14N_9 H299 IO_L15P_9 K329 IO_L15N_9 K319 IO_L16P_9 M269 IO_L16N_9 M259 IO_L25P_CC_LC_9 P329 IO_L25N_CC_LC_9 N329 IO_L26P_9 R329 IO_L26N_9 R319 IO_L27P_9 R299 IO_L27N_9 P299 IO_L28P_9 R289 IO_L28N_VREF_9 R279 IO_L29P_9 T319 IO_L29N_9 T309 IO_L30P_9 T299 IO_L30N_9 T289 IO_L31P_9 T269 IO_L31N_9 R269 IO_L32P_9 U289 IO_L32N_9 U27No Connects inFX60 DevicesNo Connects inFX40 Devices10 IO_L17P_10 N510 IO_L17N_10 N410 IO_L18P_10 P510 IO_L18N_10 P410 IO_L19P_10 P1010 IO_L19N_10 P910 IO_L20P_10 R410 IO_L20N_VREF_10 R310 IO_L21P_10 T510 IO_L21N_10 T410 IO_L22P_10 P710 IO_L22N_10 P610 IO_L23P_VRN_10 P1110 IO_L23N_VRP_10 R11134 www.xilinx.com Virtex-4 FPGA Packaging and Pinout SpecificationUG075 (v3.3) September 19, 2008

RFF1152 Flip-Chip Fine-Pitch BGA PackageTable 2-6: FF1152 Package — FX40, FX60, and FX100 Devices (Continued)BankPin DescriptionPinNumber10 IO_L24P_CC_LC_10 T610 IO_L24N_CC_LC_10 R610 IO_L1P_10 L910 IO_L1N_10 L810 IO_L2P_10 H510 IO_L2N_10 H410 IO_L3P_10 L1010 IO_L3N_10 M1010 IO_L4P_10 M810 IO_L4N_VREF_10 M710 IO_L5P_10 F510 IO_L5N_10 G510 IO_L6P_10 G310 IO_L6N_10 H310 IO_L7P_10 F410 IO_L7N_10 F310 IO_L8P_CC_LC_10 J510 IO_L8N_CC_LC_10 J410 IO_L9P_CC_LC_10 J610 IO_L9N_CC_LC_10 K610 IO_L10P_10 K410 IO_L10N_10 K310 IO_L11P_10 N1010 IO_L11N_10 N910 IO_L12P_10 N810 IO_L12N_VREF_10 N710 IO_L13P_10 L610 IO_L13N_10 L510 IO_L14P_10 L410 IO_L14N_10 L310 IO_L15P_10 M610 IO_L15N_10 M510 IO_L16P_10 M310 IO_L16N_10 N310 IO_L25P_CC_LC_10 V510 IO_L25N_CC_LC_10 U510 IO_L26P_10 U3No Connects inFX60 DevicesNo Connects inFX40 DevicesVirtex-4 FPGA Packaging and Pinout Specification www.xilinx.com 135UG075 (v3.3) September 19, 2008

Chapter 2: Pinout TablesRTable 2-6: FF1152 Package — FX40, FX60, and FX100 Devices (Continued)BankPin DescriptionPinNumber10 IO_L26N_10 T310 IO_L27P_10 U810 IO_L27N_10 T810 IO_L28P_10 R810 IO_L28N_VREF_10 R710 IO_L29P_10 T910 IO_L29N_10 R910 IO_L30P_10 V410 IO_L30N_10 V310 IO_L31P_10 T1110 IO_L31N_10 T1010 IO_L32P_10 U710 IO_L32N_10 U6No Connects inFX60 DevicesNo Connects inFX40 Devices11 IO_L17P_11 AA26 NC11 IO_L17N_11 AA25 NC11 IO_L18P_11 AC30 NC11 IO_L18N_11 AC29 NC11 IO_L19P_11 AB28 NC11 IO_L19N_11 AB27 NC11 IO_L20P_11 AB26 NC11 IO_L20N_VREF_11 AB25 NC11 IO_L21P_11 AD32 NC11 IO_L21N_11 AD31 NC11 IO_L22P_11 AD30 NC11 IO_L22N_11 AD29 NC11 IO_L23P_VRN_11 AC28 NC11 IO_L23N_VRP_11 AC27 NC11 IO_L24P_CC_LC_11 AG32 NC11 IO_L24N_CC_LC_11 AH32 NC11 IO_L1P_11 V29 NC11 IO_L1N_11 V28 NC11 IO_L2P_11 U32 NC11 IO_L2N_11 U31 NC11 IO_L3P_11 V30 NC11 IO_L3N_11 U30 NC136 www.xilinx.com Virtex-4 FPGA Packaging and Pinout SpecificationUG075 (v3.3) September 19, 2008

RFF1152 Flip-Chip Fine-Pitch BGA PackageTable 2-6: FF1152 Package — FX40, FX60, and FX100 Devices (Continued)BankPin DescriptionPinNumberNo Connects inFX60 DevicesNo Connects inFX40 Devices11 IO_L4P_11 W25 NC11 IO_L4N_VREF_11 W24 NC11 IO_L5P_11 W32 NC11 IO_L5N_11 V32 NC11 IO_L6P_11 W26 NC11 IO_L6N_11 Y26 NC11 IO_L7P_11 Y29 NC11 IO_L7N_11 W29 NC11 IO_L8P_CC_LC_11 W27 NC11 IO_L8N_CC_LC_11 V27 NC11 IO_L9P_CC_LC_11 W31 NC11 IO_L9N_CC_LC_11 W30 NC11 IO_L10P_11 Y32 NC11 IO_L10N_11 Y31 NC11 IO_L11P_11 Y28 NC11 IO_L11N_11 Y27 NC11 IO_L12P_11 Y24 NC11 IO_L12N_VREF_11 AA24 NC11 IO_L13P_11 AA31 NC11 IO_L13N_11 AA30 NC11 IO_L14P_11 AB32 NC11 IO_L14N_11 AC32 NC11 IO_L15P_11 AA29 NC11 IO_L15N_11 AA28 NC11 IO_L16P_11 AB31 NC11 IO_L16N_11 AB30 NC11 IO_L25P_CC_LC_11 AE32 NC11 IO_L25N_CC_LC_11 AE31 NC11 IO_L26P_11 AD27 NC11 IO_L26N_11 AD26 NC11 IO_L27P_11 AF31 NC11 IO_L27N_11 AF30 NC11 IO_L28P_11 AC25 NC11 IO_L28N_VREF_11 AD25 NC11 IO_L29P_11 AE29 NC11 IO_L29N_11 AF29 NC11 IO_L30P_11 AJ32 NCVirtex-4 FPGA Packaging and Pinout Specification www.xilinx.com 137UG075 (v3.3) September 19, 2008

Chapter 2: Pinout TablesRTable 2-6: FF1152 Package — FX40, FX60, and FX100 Devices (Continued)BankPin DescriptionPinNumberNo Connects inFX60 DevicesNo Connects inFX40 Devices11 IO_L30N_11 AJ31 NC11 IO_L31P_11 AG31 NC11 IO_L31N_11 AG30 NC11 IO_L32P_11 AH30 NC11 IO_L32N_11 AJ30 NC12 IO_L17P_12 AJ4 NC12 IO_L17N_12 AK3 NC12 IO_L18P_12 AE4 NC12 IO_L18N_12 AE3 NC12 IO_L19P_12 AM5 NC12 IO_L19N_12 AL5 NC12 IO_L20P_12 AC7 NC12 IO_L20N_VREF_12 AB8 NC12 IO_L21P_12 AL4 NC12 IO_L21N_12 AK4 NC12 IO_L22P_12 AF5 NC12 IO_L22N_12 AF4 NC12 IO_L23P_VRN_12 AF8 NC12 IO_L23N_VRP_12 AE7 NC12 IO_L24P_CC_LC_12 AH4 NC12 IO_L24N_CC_LC_12 AH3 NC12 IO_L1P_12 W5 NC12 IO_L1N_12 W4 NC12 IO_L2P_12 V8 NC12 IO_L2N_12 V7 NC12 IO_L3P_12 AA5 NC12 IO_L3N_12 AA4 NC12 IO_L4P_12 W7 NC12 IO_L4N_VREF_12 W6 NC12 IO_L5P_12 Y8 NC12 IO_L5N_12 Y7 NC12 IO_L6P_12 Y4 NC12 IO_L6N_12 Y3 NC12 IO_L7P_12 AC5 NC12 IO_L7N_12 AB5 NC138 www.xilinx.com Virtex-4 FPGA Packaging and Pinout SpecificationUG075 (v3.3) September 19, 2008

RFF1152 Flip-Chip Fine-Pitch BGA PackageTable 2-6: FF1152 Package — FX40, FX60, and FX100 Devices (Continued)BankPin DescriptionPinNumberNo Connects inFX60 DevicesNo Connects inFX40 Devices12 IO_L8P_CC_LC_12 AB3 NC12 IO_L8N_CC_LC_12 AA3 NC12 IO_L9P_CC_LC_12 AB7 NC12 IO_L9N_CC_LC_12 AB6 NC12 IO_L10P_12 AA6 NC12 IO_L10N_12 Y6 NC12 IO_L11P_12 AG3 NC12 IO_L11N_12 AF3 NC12 IO_L12P_12 W9 NC12 IO_L12N_VREF_12 Y9 NC12 IO_L13P_12 AA9 NC12 IO_L13N_12 AA8 NC12 IO_L14P_12 AC4 NC12 IO_L14N_12 AC3 NC12 IO_L15P_12 AF6 NC12 IO_L15N_12 AE6 NC12 IO_L16P_12 AD5 NC12 IO_L16N_12 AD4 NC12 IO_L25P_CC_LC_12 AK6 NC12 IO_L25N_CC_LC_12 AJ6 NC12 IO_L26P_12 AM3 NC12 IO_L26N_12 AL3 NC12 IO_L27P_12 AG8 NC12 IO_L27N_12 AG7 NC12 IO_L28P_12 AD7 NC12 IO_L28N_VREF_12 AD6 NC12 IO_L29P_12 AM6 NC12 IO_L29N_12 AL6 NC12 IO_L30P_12 AG6 NC12 IO_L30N_12 AG5 NC12 IO_L31P_12 AC10 NC12 IO_L31N_12 AC9 NC12 IO_L32P_12 AJ5 NC12 IO_L32N_12 AH5 NC0 VCCO_0 (1) Y15Virtex-4 FPGA Packaging and Pinout Specification www.xilinx.com 139UG075 (v3.3) September 19, 2008

Chapter 2: Pinout TablesRTable 2-6: FF1152 Package — FX40, FX60, and FX100 Devices (Continued)BankPin DescriptionPinNumber0 VCCO_0 (1) T170 VCCO_0 (1) W180 VCCO_0 (1) R201 VCCO_1 G141 VCCO_1 F172 VCCO_2 AJ182 VCCO_2 AH213 VCCO_3 K153 VCCO_3 J184 VCCO_4 AF174 VCCO_4 AE205 VCCO_5 E205 VCCO_5 H215 VCCO_5 L225 VCCO_5 D235 VCCO_5 P235 VCCO_5 G245 VCCO_5 K255 VCCO_5 C265 VCCO_5 F276 VCCO_6 D36 VCCO_6 C66 VCCO_6 F76 VCCO_6 J86 VCCO_6 E106 VCCO_6 H116 VCCO_6 L126 VCCO_6 D136 VCCO_6 C167 VCCO_7 AM197 VCCO_7 AL227 VCCO_7 AD237 VCCO_7 AG247 VCCO_7 AK257 VCCO_7 AF277 VCCO_7 AJ287 VCCO_7 AM29No Connects inFX60 DevicesNo Connects inFX40 Devices140 www.xilinx.com Virtex-4 FPGA Packaging and Pinout SpecificationUG075 (v3.3) September 19, 2008

RFF1152 Flip-Chip Fine-Pitch BGA PackageTable 2-6: FF1152 Package — FX40, FX60, and FX100 Devices (Continued)BankPin DescriptionPinNumberNo Connects inFX60 DevicesNo Connects inFX40 Devices7 VCCO_7 AL328 VCCO_8 AJ88 VCCO_8 AM98 VCCO_8 AE108 VCCO_8 AH118 VCCO_8 AA128 VCCO_8 AL128 VCCO_8 AD138 VCCO_8 AG148 VCCO_8 AK159 VCCO_9 N269 VCCO_9 T279 VCCO_9 J289 VCCO_9 M299 VCCO_9 E309 VCCO_9 R309 VCCO_9 H319 VCCO_9 L3210 VCCO_10 P310 VCCO_10 G410 VCCO_10 U410 VCCO_10 K510 VCCO_10 N610 VCCO_10 T710 VCCO_10 M910 VCCO_10 R1011 VCCO_11 Y25 NC11 VCCO_11 AC26 NC11 VCCO_11 W28 NC11 VCCO_11 AB29 NC11 VCCO_11 AE30 NC11 VCCO_11 V31 NC11 VCCO_11 AH31 NC11 VCCO_11 AA32 NC12 VCCO_12 AD3 NC12 VCCO_12 AG4 NC12 VCCO_12 Y5 NCVirtex-4 FPGA Packaging and Pinout Specification www.xilinx.com 141UG075 (v3.3) September 19, 2008

Chapter 2: Pinout TablesRTable 2-6: FF1152 Package — FX40, FX60, and FX100 Devices (Continued)BankPin DescriptionPinNumberNo Connects inFX60 DevicesNo Connects inFX40 Devices12 VCCO_12 AK5 NC12 VCCO_12 AC6 NC12 VCCO_12 AF7 NC12 VCCO_12 W8 NC12 VCCO_12 AB9 NC101 AVCCAUXRXA_101 B21 NC NC101 RXPPADA_101 A20 NC NC101 VTRXA_101 A22 NC NC101 RXNPADA_101 A21 NC NC101 AVCCAUXMGT_101 B28 NC NC101 AVCCAUXTX_101 B25 NC NC101 VTTXA_101 B23 NC NC101 TXPPADA_101 A23 NC NC101 TXNPADA_101 A24 NC NC101 VTTXB_101 B26 NC NC101 TXPPADB_101 A25 NC NC101 TXNPADB_101 A26 NC NC101 AVCCAUXRXB_101 B30 NC NC101 RXPPADB_101 A28 NC NC101 VTRXB_101 A27 NC NC101 RXNPADB_101 A29 NC NC102 AVCCAUXRXA_102 B32102 RXPPADA_102 A31102 VTRXA_102 C34102 RXNPADA_102 A32102 AVCCAUXMGT_102 J33102 AVCCAUXTX_102 F33102 VTTXA_102 D33102 TXPPADA_102 D34102 TXNPADA_102 E34102 VTTXB_102 G33102 TXPPADB_102 F34102 TXNPADB_102 G34102 AVCCAUXRXB_102 K33142 www.xilinx.com Virtex-4 FPGA Packaging and Pinout SpecificationUG075 (v3.3) September 19, 2008

RFF1152 Flip-Chip Fine-Pitch BGA PackageTable 2-6: FF1152 Package — FX40, FX60, and FX100 Devices (Continued)BankPin DescriptionPinNumber102 RXPPADB_102 J34102 VTRXB_102 H34102 RXNPADB_102 K34102 MGTCLK_P_102 M34102 MGTCLK_N_102 N34No Connects inFX60 DevicesNo Connects inFX40 Devices103 AVCCAUXRXA_103 T33103 RXPPADA_103 R34103 VTRXA_103 U34103 RXNPADA_103 T34103 AVCCAUXMGT_103 AC33103 AVCCAUXTX_103 Y33103 VTTXA_103 V33103 TXPPADA_103 V34103 TXNPADA_103 W34103 VTTXB_103 AA33103 TXPPADB_103 Y34103 TXNPADB_103 AA34103 AVCCAUXRXB_103 AE33103 RXPPADB_103 AC34103 VTRXB_103 AB34103 RXNPADB_103 AD34105 AVCCAUXRXA_105 AG33105 RXPPADA_105 AF34105 VTRXA_105 AH34105 RXNPADA_105 AG34105 AVCCAUXMGT_105 AN32105 AVCCAUXTX_105 AL33105 VTTXA_105 AJ33105 TXPPADA_105 AJ34105 TXNPADA_105 AK34105 VTTXB_105 AM33105 TXPPADB_105 AL34105 TXNPADB_105 AM34105 AVCCAUXRXB_105 AN31Virtex-4 FPGA Packaging and Pinout Specification www.xilinx.com 143UG075 (v3.3) September 19, 2008

Chapter 2: Pinout TablesRTable 2-6: FF1152 Package — FX40, FX60, and FX100 Devices (Continued)BankPin DescriptionPinNumber105 RXPPADB_105 AP32105 VTRXB_105 AN33105 RXNPADB_105 AP31105 MGTCLK_P_105 AP29105 MGTCLK_N_105 AP28105 RTERM_105 AN29105 MGTVREF_105 AN27No Connects inFX60 DevicesNo Connects inFX40 Devices106 AVCCAUXRXA_106 AN25 NC106 RXPPADA_106 AP26 NC106 VTRXA_106 AP24 NC106 RXNPADA_106 AP25 NC106 AVCCAUXMGT_106 AN18 NC106 AVCCAUXTX_106 AN22 NC106 VTTXA_106 AN23 NC106 TXPPADA_106 AP23 NC106 TXNPADA_106 AP22 NC106 VTTXB_106 AN20 NC106 TXPPADB_106 AP21 NC106 TXNPADB_106 AP20 NC106 AVCCAUXRXB_106 AN17 NC106 RXPPADB_106 AP18 NC106 VTRXB_106 AP19 NC106 RXNPADB_106 AP17 NC109 AVCCAUXRXA_109 AN7 NC109 RXPPADA_109 AP6 NC109 VTRXA_109 AP8 NC109 RXNPADA_109 AP7 NC109 AVCCAUXMGT_109 AN14 NC109 AVCCAUXTX_109 AN10 NC109 VTTXA_109 AN9 NC109 TXPPADA_109 AP9 NC109 TXNPADA_109 AP10 NC109 VTTXB_109 AN12 NC109 TXPPADB_109 AP11 NC144 www.xilinx.com Virtex-4 FPGA Packaging and Pinout SpecificationUG075 (v3.3) September 19, 2008

RFF1152 Flip-Chip Fine-Pitch BGA PackageTable 2-6: FF1152 Package — FX40, FX60, and FX100 Devices (Continued)BankPin DescriptionPinNumberNo Connects inFX60 DevicesNo Connects inFX40 Devices109 TXNPADB_109 AP12 NC109 AVCCAUXRXB_109 AN15 NC109 RXPPADB_109 AP14 NC109 VTRXB_109 AP13 NC109 RXNPADB_109 AP15 NC110 AVCCAUXRXA_110 AD2110 RXPPADA_110 AC1110 VTRXA_110 AE1110 RXNPADA_110 AD1110 AVCCAUXMGT_110 AL2110 AVCCAUXTX_110 AH2110 VTTXA_110 AF2110 TXPPADA_110 AF1110 TXNPADA_110 AG1110 VTTXB_110 AJ2110 TXPPADB_110 AH1110 TXNPADB_110 AJ1110 AVCCAUXRXB_110 AM2110 RXPPADB_110 AL1110 VTRXB_110 AK1110 RXNPADB_110 AM1110 MGTCLK_P_110 AP3110 MGTCLK_N_110 AP4110 RTERM_110 AN3110 MGTVREF_110 AN5112 AVCCAUXRXA_112 N2112 RXPPADA_112 M1112 VTRXA_112 P1112 RXNPADA_112 N1112 AVCCAUXMGT_112 Y2112 AVCCAUXTX_112 U2112 VTTXA_112 R2112 TXPPADA_112 R1112 TXNPADA_112 T1Virtex-4 FPGA Packaging and Pinout Specification www.xilinx.com 145UG075 (v3.3) September 19, 2008

Chapter 2: Pinout TablesRTable 2-6: FF1152 Package — FX40, FX60, and FX100 Devices (Continued)BankPin DescriptionPinNumber112 VTTXB_112 V2112 TXPPADB_112 U1112 TXNPADB_112 V1112 AVCCAUXRXB_112 AB2112 RXPPADB_112 Y1112 VTRXB_112 W1112 RXNPADB_112 AA1No Connects inFX60 DevicesNo Connects inFX40 Devices113 AVCCAUXRXA_113 B6113 RXPPADA_113 A7113 VTRXA_113 A5113 RXNPADA_113 A6113 AVCCAUXMGT_113 F2113 AVCCAUXTX_113 C2113 VTTXA_113 B4113 TXPPADA_113 A4113 TXNPADA_113 A3113 VTTXB_113 D2113 TXPPADB_113 C1113 TXNPADB_113 D1113 AVCCAUXRXB_113 G2113 RXPPADB_113 F1113 VTRXB_113 E1113 RXNPADB_113 G1113 MGTCLK_P_113 J1113 MGTCLK_N_113 K1114 AVCCAUXRXA_114 B17 NC NC114 RXPPADA_114 A18 NC NC114 VTRXA_114 A16 NC NC114 RXNPADA_114 A17 NC NC114 AVCCAUXMGT_114 B10 NC NC114 AVCCAUXTX_114 B13 NC NC114 VTTXA_114 B15 NC NC114 TXPPADA_114 A15 NC NC114 TXNPADA_114 A14 NC NC146 www.xilinx.com Virtex-4 FPGA Packaging and Pinout SpecificationUG075 (v3.3) September 19, 2008

RFF1152 Flip-Chip Fine-Pitch BGA PackageTable 2-6: FF1152 Package — FX40, FX60, and FX100 Devices (Continued)BankPin DescriptionPinNumberNo Connects inFX60 DevicesNo Connects inFX40 Devices114 VTTXB_114 B12 NC NC114 TXPPADB_114 A13 NC NC114 TXNPADB_114 A12 NC NC114 AVCCAUXRXB_114 B8 NC NC114 RXPPADB_114 A10 NC NC114 VTRXB_114 A11 NC NC114 RXNPADB_114 A9 NC NC101 GNDA_101 A19 NC NC101 GNDA_101 B20 NC NC101 GNDA_101 B22 NC NC101 GNDA_101 B24 NC NC101 GNDA_101 B27 NC NC101 GNDA_101 B29 NC NC102 GNDA_102 A30102 GNDA_102 B31102 GNDA_102 A33102 GNDA_102 B33102 GNDA_102 C33102 GNDA_102 E33102 GNDA_102 H33102 GNDA_102 L33102 GNDA_102 M33102 GNDA_102 N33102 GNDA_102 P33102 GNDA_102 B34102 GNDA_102 L34102 GNDA_102 P34103 GNDA_103 R33103 GNDA_103 U33103 GNDA_103 W33103 GNDA_103 AB33103 GNDA_103 AD33103 GNDA_103 AE34105 GNDA_105 AP27105 GNDA_105 AN28Virtex-4 FPGA Packaging and Pinout Specification www.xilinx.com 147UG075 (v3.3) September 19, 2008

Chapter 2: Pinout TablesRTable 2-6: FF1152 Package — FX40, FX60, and FX100 Devices (Continued)BankPin DescriptionPinNumberNo Connects inFX60 DevicesNo Connects inFX40 Devices105 GNDA_105 AN30105 GNDA_105 AP30105 GNDA_105 AF33105 GNDA_105 AH33105 GNDA_105 AK33105 GNDA_105 AP33105 GNDA_105 AN34106 GNDA_106 AP16 NC106 GNDA_106 AN19 NC106 GNDA_106 AN21 NC106 GNDA_106 AN24 NC106 GNDA_106 AN26 NC109 GNDA_109 AN6 NC109 GNDA_109 AN8 NC109 GNDA_109 AN11 NC109 GNDA_109 AN13 NC109 GNDA_109 AN16 NC110 GNDA_110 AN1110 GNDA_110 AC2110 GNDA_110 AE2110 GNDA_110 AG2110 GNDA_110 AK2110 GNDA_110 AN2110 GNDA_110 AP2110 GNDA_110 AN4110 GNDA_110 AP5112 GNDA_112 AA2112 GNDA_112 AB1112 GNDA_112 M2112 GNDA_112 P2112 GNDA_112 T2112 GNDA_112 W2113 GNDA_113 B1113 GNDA_113 H1113 GNDA_113 L1113 GNDA_113 A2113 GNDA_113 B2148 www.xilinx.com Virtex-4 FPGA Packaging and Pinout SpecificationUG075 (v3.3) September 19, 2008

RFF1152 Flip-Chip Fine-Pitch BGA PackageTable 2-6: FF1152 Package — FX40, FX60, and FX100 Devices (Continued)BankPin DescriptionPinNumberNo Connects inFX60 DevicesNo Connects inFX40 Devices113 GNDA_113 E2113 GNDA_113 H2113 GNDA_113 J2113 GNDA_113 K2113 GNDA_113 L2113 GNDA_113 B3113 GNDA_113 B5113 GNDA_113 B7113 GNDA_113 A8114 GNDA_114 B9 NC NC114 GNDA_114 B11 NC NC114 GNDA_114 B14 NC NC114 GNDA_114 B16 NC NC114 GNDA_114 B18 NC NC114 GNDA_114 B19 NC NCN/A VREFN_SM (2) AL17N/A VREFP_SM (2) AL16N/A AVDD_SM (3) AL15N/A VN_SM (2) AM17N/A VP_SM (2) AM16N/A AVSS_SM (2) AM15N/A VREFN_ADC (2) D20 NCN/A VREFP_ADC (2) D19 NCN/A AVDD_ADC (3) D18 NCN/A VN_ADC (2) C20 NCN/A VP_ADC (2) C19 NCN/A AVSS_ADC (2) C18 NCN/A GND J3N/A GND W3N/A GND AJ3N/A GND M4N/A GND AB4N/A GND AM4N/A GND E5Virtex-4 FPGA Packaging and Pinout Specification www.xilinx.com 149UG075 (v3.3) September 19, 2008

Chapter 2: Pinout TablesRTable 2-6: FF1152 Package — FX40, FX60, and FX100 Devices (Continued)BankPin DescriptionPinNumberN/A GND R5N/A GND AE5N/A GND H6N/A GND V6N/A GND AH6N/A GND L7N/A GND AA7N/A GND AL7N/A GND D8N/A GND P8N/A GND AD8N/A GND G9N/A GND U9N/A GND AG9N/A GND K10N/A GND V10N/A GND Y10N/A GND AK10N/A GND C11N/A GND N11N/A GND W11N/A GND AC11N/A GND F12N/A GND P12N/A GND T12N/A GND V12N/A GND Y12N/A GND AF12N/A GND J13N/A GND R13N/A GND U13N/A GND W13N/A GND AJ13N/A GND M14N/A GND P14N/A GND V14N/A GND AB14No Connects inFX60 DevicesNo Connects inFX40 Devices150 www.xilinx.com Virtex-4 FPGA Packaging and Pinout SpecificationUG075 (v3.3) September 19, 2008

RFF1152 Flip-Chip Fine-Pitch BGA PackageTable 2-6: FF1152 Package — FX40, FX60, and FX100 Devices (Continued)BankPin DescriptionPinNumberN/A GND AM14N/A GND E15N/A GND N15N/A GND R15N/A GND U15N/A GND AC15N/A GND AE15N/A GND H16N/A GND P16N/A GND V16N/A GND Y16N/A GND AH16N/A GND L17N/A GND N17N/A GND U17N/A GND AA17N/A GND AC17N/A GND M18N/A GND P18N/A GND AB18N/A GND AD18N/A GND AM18N/A GND G19N/A GND U19N/A GND AA19N/A GND AG19N/A GND K20N/A GND M20N/A GND V20N/A GND Y20N/A GND AB20N/A GND AK20N/A GND C21N/A GND N21N/A GND U21N/A GND AA21N/A GND AC21No Connects inFX60 DevicesNo Connects inFX40 DevicesVirtex-4 FPGA Packaging and Pinout Specification www.xilinx.com 151UG075 (v3.3) September 19, 2008

Chapter 2: Pinout TablesRTable 2-6: FF1152 Package — FX40, FX60, and FX100 Devices (Continued)BankPin DescriptionPinNumberN/A GND F22N/A GND T22N/A GND V22N/A GND Y22N/A GND AF22N/A GND J23N/A GND R23N/A GND U23N/A GND W23N/A GND AA23N/A GND AJ23N/A GND M24N/A GND T24N/A GND AB24N/A GND AM24N/A GND E25N/A GND R25N/A GND U25N/A GND AE25N/A GND H26N/A GND V26N/A GND AH26N/A GND L27N/A GND AA27N/A GND AL27N/A GND D28N/A GND P28N/A GND AD28N/A GND G29N/A GND U29N/A GND AG29N/A GND K30N/A GND Y30N/A GND AK30N/A GND C31N/A GND N31N/A GND AC31No Connects inFX60 DevicesNo Connects inFX40 Devices152 www.xilinx.com Virtex-4 FPGA Packaging and Pinout SpecificationUG075 (v3.3) September 19, 2008

RFF1152 Flip-Chip Fine-Pitch BGA PackageTable 2-6: FF1152 Package — FX40, FX60, and FX100 Devices (Continued)BankPin DescriptionPinNumberN/A GND F32N/A GND T32N/A GND AF32No Connects inFX60 DevicesNo Connects inFX40 DevicesN/A VCCAUX AE8N/A VCCAUX V9N/A VCCAUX AB10N/A VCCAUX U11N/A VCCAUX N13N/A VCCAUX T14N/A VCCAUX M16N/A VCCAUX U16N/A VCCAUX AB16N/A VCCAUX AD16N/A VCCAUX L19N/A VCCAUX N19N/A VCCAUX V19N/A VCCAUX AC19N/A VCCAUX W21N/A VCCAUX AB22N/A VCCAUX V24N/A VCCAUX N25N/A VCCAUX U26N/A VCCAUX K27N/A VCCINT AC8N/A VCCINT U10N/A VCCINT W10N/A VCCINT AA10N/A VCCINT V11N/A VCCINT Y11N/A VCCINT N12N/A VCCINT R12N/A VCCINT U12N/A VCCINT W12N/A VCCINT P13N/A VCCINT T13Virtex-4 FPGA Packaging and Pinout Specification www.xilinx.com 153UG075 (v3.3) September 19, 2008

Chapter 2: Pinout TablesRTable 2-6: FF1152 Package — FX40, FX60, and FX100 Devices (Continued)BankPin DescriptionPinNumberN/A VCCINT V13N/A VCCINT Y13N/A VCCINT N14N/A VCCINT R14N/A VCCINT U14N/A VCCINT W14N/A VCCINT AC14N/A VCCINT M15N/A VCCINT P15N/A VCCINT T15N/A VCCINT V15N/A VCCINT AB15N/A VCCINT AD15N/A VCCINT N16N/A VCCINT R16N/A VCCINT W16N/A VCCINT AC16N/A VCCINT M17N/A VCCINT P17N/A VCCINT V17N/A VCCINT Y17N/A VCCINT AB17N/A VCCINT AD17N/A VCCINT L18N/A VCCINT N18N/A VCCINT R18N/A VCCINT U18N/A VCCINT AA18N/A VCCINT AC18N/A VCCINT M19N/A VCCINT T19N/A VCCINT Y19N/A VCCINT AB19N/A VCCINT L20N/A VCCINT N20N/A VCCINT U20N/A VCCINT W20No Connects inFX60 DevicesNo Connects inFX40 Devices154 www.xilinx.com Virtex-4 FPGA Packaging and Pinout SpecificationUG075 (v3.3) September 19, 2008

RFF1152 Flip-Chip Fine-Pitch BGA PackageTable 2-6: FF1152 Package — FX40, FX60, and FX100 Devices (Continued)BankPin DescriptionPinNumberNo Connects inFX60 DevicesNo Connects inFX40 DevicesN/A VCCINT AA20N/A VCCINT AC20N/A VCCINT M21N/A VCCINT T21N/A VCCINT V21N/A VCCINT Y21N/A VCCINT AB21N/A VCCINT R22N/A VCCINT U22N/A VCCINT W22N/A VCCINT AA22N/A VCCINT T23N/A VCCINT V23N/A VCCINT Y23N/A VCCINT AB23N/A VCCINT R24N/A VCCINT U24N/A VCCINT AC24N/A VCCINT P25N/A VCCINT T25N/A VCCINT V25N/A VCCINT M27Notes:1. This voltage is also referred to as V CC_CONFIG in the Virtex-4 Configuration Guide.2. Connect this reserved pin to GND.3. Connect this reserved pin to 2.5V (sharing the same PCB supply distribution as V CCAUX is acceptable).Virtex-4 FPGA Packaging and Pinout Specification www.xilinx.com 155UG075 (v3.3) September 19, 2008

Chapter 2: Pinout TablesRFF1513 Flip-Chip Fine-Pitch BGA PackageAs shown in Table 2-7, Virtex-4 XC4VLX100, XC4VLX160, and XC4VLX200 devices areavailable in the FF1513 flip-chip fine-pitch BGA package. Pinouts in each of these devicesare identical.To be assured of having the very latest Virtex-4 FPGA pinout information, visitwww.xilinx.com and check for any updates to this document. ASCII package pinout filesare also available for download from the Xilinx website.Table 2-7: FF1513 Package — LX100, LX160, and LX200 DevicesBank Pin Description Pin Number0 HSWAPEN_0 V230 CCLK_0 W200 D_IN_0 Y160 PROG_B_0 W220 INIT_B_0 V240 CS_B_0 Y170 DONE_0 Y190 RDWR_B_0 Y180 VBATT_0 W240 M2_0 Y220 PWRDWN_B_0 Y210 TMS_0 AA160 M0_0 Y230 TDO_0 AB160 TCK_0 AA180 M1_0 Y240 DOUT_BUSY_0 AA200 TDI_0 AB170 TDN_0 H190 TDP_0 H201 IO_L1P_D31_LC_1 F261 IO_L1N_D30_LC_1 F251 IO_L2P_D29_LC_1 K161 IO_L2N_D28_LC_1 L161 IO_L3P_D27_LC_1 E261 IO_L3N_D26_LC_1 D261 IO_L4P_D25_LC_1 J161 IO_L4N_D24_VREF_LC_1 H151 IO_L5P_D23_LC_1 M251 IO_L5N_D22_LC_1 N24156 www.xilinx.com Virtex-4 FPGA Packaging and Pinout SpecificationUG075 (v3.3) September 19, 2008

RFF1513 Flip-Chip Fine-Pitch BGA PackageTable 2-7: FF1513 Package — LX100, LX160, and LX200 Devices (Continued)Bank Pin Description Pin Number1 IO_L6P_D21_LC_1 G161 IO_L6N_D20_LC_1 G151 IO_L7P_D19_LC_1 T231 IO_L7N_D18_LC_1 R221 IO_L8P_D17_CC_LC_1 A161 IO_L8N_D16_CC_LC_1 B161 IO_L9P_GC_LC_1 C201 IO_L9N_GC_LC_1 D201 IO_L10P_GC_LC_1 D191 IO_L10N_GC_LC_1 E191 IO_L11P_GC_LC_1 E211 IO_L11N_GC_LC_1 D211 IO_L12P_GC_LC_1 C191 IO_L12N_GC_VREF_LC_1 C181 IO_L13P_GC_LC_1 D221 IO_L13N_GC_LC_1 C221 IO_L14P_GC_LC_1 G201 IO_L14N_GC_LC_1 F191 IO_L15P_GC_LC_1 J221 IO_L15N_GC_LC_1 H221 IO_L16P_GC_CC_LC_1 T201 IO_L16N_GC_CC_LC_1 T191 IO_L17P_CC_LC_1 G221 IO_L17N_CC_LC_1 F211 IO_L18P_VRN_LC_1 P191 IO_L18N_VRP_LC_1 N181 IO_L19P_LC_1 H231 IO_L19N_LC_1 G231 IO_L20P_LC_1 L181 IO_L20N_VREF_LC_1 M181 IO_L21P_LC_1 F231 IO_L21N_LC_1 E221 IO_L22P_LC_1 G181 IO_L22N_LC_1 H171 IO_L23P_LC_1 C231 IO_L23N_LC_1 B231 IO_L24P_LC_1 E181 IO_L24N_LC_1 F18Virtex-4 FPGA Packaging and Pinout Specification www.xilinx.com 157UG075 (v3.3) September 19, 2008

Chapter 2: Pinout TablesRTable 2-7: FF1513 Package — LX100, LX160, and LX200 Devices (Continued)Bank Pin Description Pin Number1 IO_L25P_LC_1 F241 IO_L25N_LC_1 E241 IO_L26P_LC_1 A181 IO_L26N_LC_1 B181 IO_L27P_LC_1 D241 IO_L27N_LC_1 C241 IO_L28P_LC_1 U201 IO_L28N_VREF_LC_1 U181 IO_L29P_LC_1 A241 IO_L29N_LC_1 A231 IO_L30P_LC_1 T181 IO_L30N_LC_1 R181 IO_L31P_LC_1 N231 IO_L31N_LC_1 M231 IO_L32P_CC_LC_1 P171 IO_L32N_CC_LC_1 R171 IO_L33P_CC_LC_1 L241 IO_L33N_CC_LC_1 K231 IO_L34P_LC_1 M171 IO_L34N_LC_1 N171 IO_L35P_LC_1 K241 IO_L35N_LC_1 J241 IO_L36P_LC_1 J171 IO_L36N_VREF_LC_1 K171 IO_L37P_LC_1 D251 IO_L37N_LC_1 C251 IO_L38P_LC_1 D171 IO_L38N_LC_1 E171 IO_L39P_LC_1 B251 IO_L39N_LC_1 A251 IO_L40P_LC_1 B171 IO_L40N_LC_1 C172 IO_L1P_D15_CC_LC_2 AN252 IO_L1N_D14_CC_LC_2 AN242 IO_L2P_D13_LC_2 AT142 IO_L2N_D12_LC_2 AR142 IO_L3P_D11_LC_2 AV24158 www.xilinx.com Virtex-4 FPGA Packaging and Pinout SpecificationUG075 (v3.3) September 19, 2008

RFF1513 Flip-Chip Fine-Pitch BGA PackageTable 2-7: FF1513 Package — LX100, LX160, and LX200 Devices (Continued)Bank Pin Description Pin Number2 IO_L3N_D10_LC_2 AW242 IO_L4P_D9_LC_2 AV152 IO_L4N_D8_VREF_LC_2 AU152 IO_L5P_D7_LC_2 AL242 IO_L5N_D6_LC_2 AM252 IO_L6P_D5_LC_2 AP152 IO_L6N_D4_LC_2 AP142 IO_L7P_D3_LC_2 AJ242 IO_L7N_D2_LC_2 AK242 IO_L8P_D1_LC_2 AH152 IO_L8N_D0_LC_2 AG162 IO_L9P_GC_CC_LC_2 AP222 IO_L9N_GC_CC_LC_2 AR222 IO_L10P_GC_LC_2 AM182 IO_L10N_GC_LC_2 AL182 IO_L11P_GC_LC_2 AT212 IO_L11N_GC_LC_2 AR212 IO_L12P_GC_LC_2 AT192 IO_L12N_GC_VREF_LC_2 AR192 IO_L13P_GC_LC_2 AP212 IO_L13N_GC_LC_2 AN202 IO_L14P_GC_LC_2 AP192 IO_L14N_GC_LC_2 AR182 IO_L15P_GC_LC_2 AM212 IO_L15N_GC_LC_2 AM202 IO_L16P_GC_LC_2 AU202 IO_L16N_GC_LC_2 AT202 IO_L17P_LC_2 AG222 IO_L17N_LC_2 AF212 IO_L18P_LC_2 AH172 IO_L18N_LC_2 AG172 IO_L19P_LC_2 AE222 IO_L19N_LC_2 AD212 IO_L20P_LC_2 AE182 IO_L20N_VREF_LC_2 AD172 IO_L21P_LC_2 AV222 IO_L21N_LC_2 AW222 IO_L22P_LC_2 AU18Virtex-4 FPGA Packaging and Pinout Specification www.xilinx.com 159UG075 (v3.3) September 19, 2008

Chapter 2: Pinout TablesRTable 2-7: FF1513 Package — LX100, LX160, and LX200 Devices (Continued)Bank Pin Description Pin Number2 IO_L22N_LC_2 AT182 IO_L23P_VRN_LC_2 AU222 IO_L23N_VRP_LC_2 AU212 IO_L24P_CC_LC_2 AN182 IO_L24N_CC_LC_2 AP172 IO_L25P_CC_LC_2 AM232 IO_L25N_CC_LC_2 AN222 IO_L26P_LC_2 AW172 IO_L26N_LC_2 AV172 IO_L27P_LC_2 AK232 IO_L27N_LC_2 AL232 IO_L28P_LC_2 AU172 IO_L28N_VREF_LC_2 AU162 IO_L29P_LC_2 AG232 IO_L29N_LC_2 AH232 IO_L30P_LC_2 AN172 IO_L30N_LC_2 AM172 IO_L31P_LC_2 AH222 IO_L31N_LC_2 AJ222 IO_L32P_LC_2 AK172 IO_L32N_LC_2 AL162 IO_L33P_LC_2 AE232 IO_L33N_LC_2 AF232 IO_L34P_LC_2 AW162 IO_L34N_LC_2 AW152 IO_L35P_LC_2 AC222 IO_L35N_LC_2 AC202 IO_L36P_LC_2 AT162 IO_L36N_VREF_LC_2 AT152 IO_L37P_LC_2 AU232 IO_L37N_LC_2 AV232 IO_L38P_LC_2 AR162 IO_L38N_LC_2 AP162 IO_L39P_LC_2 AR232 IO_L39N_LC_2 AT232 IO_L40P_CC_LC_2 AK162 IO_L40N_CC_LC_2 AJ16160 www.xilinx.com Virtex-4 FPGA Packaging and Pinout SpecificationUG075 (v3.3) September 19, 2008

RFF1513 Flip-Chip Fine-Pitch BGA PackageTable 2-7: FF1513 Package — LX100, LX160, and LX200 Devices (Continued)Bank Pin Description Pin Number3 IO_L1P_GC_CC_LC_3 P203 IO_L1N_GC_CC_LC_3 N203 IO_L2P_GC_VRN_LC_3 J193 IO_L2N_GC_VRP_LC_3 K193 IO_L3P_GC_LC_3 N223 IO_L3N_GC_LC_3 M223 IO_L4P_GC_LC_3 J213 IO_L4N_GC_VREF_LC_3 J203 IO_L5P_GC_LC_3 M213 IO_L5N_GC_LC_3 M203 IO_L6P_GC_LC_3 L203 IO_L6N_GC_LC_3 L193 IO_L7P_GC_LC_3 P223 IO_L7N_GC_LC_3 P213 IO_L8P_GC_LC_3 L213 IO_L8N_GC_LC_3 K214 IO_L1P_GC_LC_4 AH204 IO_L1N_GC_LC_4 AH194 IO_L2P_GC_LC_4 AF194 IO_L2N_GC_LC_4 AF184 IO_L3P_GC_LC_4 AJ214 IO_L3N_GC_LC_4 AJ204 IO_L4P_GC_LC_4 AG204 IO_L4N_GC_VREF_LC_4 AF204 IO_L5P_GC_LC_4 AL204 IO_L5N_GC_LC_4 AL194 IO_L6P_GC_LC_4 AH184 IO_L6N_GC_LC_4 AG184 IO_L7P_GC_VRN_LC_4 AL214 IO_L7N_GC_VRP_LC_4 AK214 IO_L8P_GC_CC_LC_4 AK194 IO_L8N_GC_CC_LC_4 AJ195 IO_L1P_ADC7_5 B265 IO_L1N_ADC7_5 A265 IO_L2P_ADC6_5 E285 IO_L2N_ADC6_5 F28Virtex-4 FPGA Packaging and Pinout Specification www.xilinx.com 161UG075 (v3.3) September 19, 2008

Chapter 2: Pinout TablesRTable 2-7: FF1513 Package — LX100, LX160, and LX200 Devices (Continued)Bank Pin Description Pin Number5 IO_L3P_ADC5_5 E275 IO_L3N_ADC5_5 D275 IO_L4P_5 A305 IO_L4N_VREF_5 A315 IO_L5P_ADC4_5 G255 IO_L5N_ADC4_5 G265 IO_L6P_ADC3_5 D295 IO_L6N_ADC3_5 E295 IO_L7P_ADC2_5 A285 IO_L7N_ADC2_5 A295 IO_L8P_CC_ADC1_LC_5 D305 IO_L8N_CC_ADC1_LC_5 D315 IO_L17P_5 H255 IO_L17N_5 J265 IO_L18P_5 G305 IO_L18N_5 H295 IO_L19P_5 B325 IO_L19N_5 B335 IO_L20P_5 J295 IO_L20N_VREF_5 K295 IO_L21P_5 B305 IO_L21N_5 B315 IO_L22P_5 C335 IO_L22N_5 C345 IO_L23P_VRN_5 F315 IO_L23N_VRP_5 G315 IO_L24P_CC_LC_5 B355 IO_L24N_CC_LC_5 C355 IO_L9P_CC_LC_5 C275 IO_L9N_CC_LC_5 B275 IO_L10P_5 F295 IO_L10N_5 G285 IO_L11P_5 J275 IO_L11N_5 H275 IO_L12P_5 C325 IO_L12N_VREF_5 D325 IO_L13P_5 B285 IO_L13N_5 C28162 www.xilinx.com Virtex-4 FPGA Packaging and Pinout SpecificationUG075 (v3.3) September 19, 2008

RFF1513 Flip-Chip Fine-Pitch BGA PackageTable 2-7: FF1513 Package — LX100, LX160, and LX200 Devices (Continued)Bank Pin Description Pin Number5 IO_L14P_5 A335 IO_L14N_5 A345 IO_L15P_5 C295 IO_L15N_5 C305 IO_L16P_5 E315 IO_L16N_5 E325 IO_L25P_CC_LC_5 M275 IO_L25N_CC_LC_5 L285 IO_L26P_5 E335 IO_L26N_5 F335 IO_L27P_5 H305 IO_L27N_5 J305 IO_L28P_5 G325 IO_L28N_VREF_5 G335 IO_L29P_5 A355 IO_L29N_5 A365 IO_L30P_5 J315 IO_L30N_5 K315 IO_L31P_5 B365 IO_L31N_5 B375 IO_L32P_5 L305 IO_L32N_5 L316 IO_L1P_6 A146 IO_L1N_6 A136 IO_L2P_6 E126 IO_L2N_6 E116 IO_L3P_6 B136 IO_L3N_6 C136 IO_L4P_6 D116 IO_L4N_VREF_6 D106 IO_L5P_6 D146 IO_L5N_6 C146 IO_L6P_6 A116 IO_L6N_6 A106 IO_L7P_6 E136 IO_L7N_6 F136 IO_L8P_CC_LC_6 B10Virtex-4 FPGA Packaging and Pinout Specification www.xilinx.com 163UG075 (v3.3) September 19, 2008

Chapter 2: Pinout TablesRTable 2-7: FF1513 Package — LX100, LX160, and LX200 Devices (Continued)Bank Pin Description Pin Number6 IO_L8N_CC_LC_6 C106 IO_L17P_6 J146 IO_L17N_6 H136 IO_L18P_6 E96 IO_L18N_6 F96 IO_L19P_6 C126 IO_L19N_6 D126 IO_L20P_6 B76 IO_L20N_VREF_6 C76 IO_L21P_6 D156 IO_L21N_6 C156 IO_L22P_6 G106 IO_L22N_6 H106 IO_L23P_VRN_6 A96 IO_L23N_VRP_6 A86 IO_L24P_CC_LC_6 E86 IO_L24N_CC_LC_6 F86 IO_L9P_CC_LC_6 F146 IO_L9N_CC_LC_6 E146 IO_L10P_6 H126 IO_L10N_6 J126 IO_L11P_6 G136 IO_L11N_6 G126 IO_L12P_6 C96 IO_L12N_VREF_6 D96 IO_L13P_6 B156 IO_L13N_6 A156 IO_L14P_6 F116 IO_L14N_6 G116 IO_L15P_6 B126 IO_L15N_6 B116 IO_L16P_6 B86 IO_L16N_6 C86 IO_L25P_CC_LC_6 E166 IO_L25N_CC_LC_6 D166 IO_L26P_6 D76 IO_L26N_6 E76 IO_L27P_6 A6164 www.xilinx.com Virtex-4 FPGA Packaging and Pinout SpecificationUG075 (v3.3) September 19, 2008

RFF1513 Flip-Chip Fine-Pitch BGA PackageTable 2-7: FF1513 Package — LX100, LX160, and LX200 Devices (Continued)Bank Pin Description Pin Number6 IO_L27N_6 B66 IO_L28P_6 J106 IO_L28N_VREF_6 J96 IO_L29P_6 F166 IO_L29N_6 F156 IO_L30P_6 H96 IO_L30N_6 G86 IO_L31P_6 K116 IO_L31N_6 L116 IO_L32P_6 L106 IO_L32N_6 K97 IO_L25P_CC_SM7_LC_7 AP277 IO_L25N_CC_SM7_LC_7 AR277 IO_L26P_SM6_7 AV307 IO_L26N_SM6_7 AU307 IO_L27P_SM5_7 AR267 IO_L27N_SM5_7 AT267 IO_L28P_7 AW297 IO_L28N_VREF_7 AV297 IO_L29P_SM4_7 AV277 IO_L29N_SM4_7 AW277 IO_L30P_SM3_7 AT297 IO_L30N_SM3_7 AR297 IO_L31P_SM2_7 AU267 IO_L31N_SM2_7 AU277 IO_L32P_SM1_7 AT287 IO_L32N_SM1_7 AR287 IO_L17P_7 AL267 IO_L17N_7 AM277 IO_L18P_7 AU317 IO_L18N_7 AU327 IO_L19P_7 AV287 IO_L19N_7 AU287 IO_L20P_7 AW327 IO_L20N_VREF_7 AV327 IO_L21P_7 AW257 IO_L21N_7 AW26Virtex-4 FPGA Packaging and Pinout Specification www.xilinx.com 165UG075 (v3.3) September 19, 2008

Chapter 2: Pinout TablesRTable 2-7: FF1513 Package — LX100, LX160, and LX200 Devices (Continued)Bank Pin Description Pin Number7 IO_L22P_7 AP297 IO_L22N_7 AN297 IO_L23P_VRN_7 AN277 IO_L23N_VRP_7 AN287 IO_L24P_CC_LC_7 AL287 IO_L24N_CC_LC_7 AM287 IO_L1P_7 AT337 IO_L1N_7 AR337 IO_L2P_7 AJ307 IO_L2N_7 AK317 IO_L3P_7 AM307 IO_L3N_7 AL307 IO_L4P_7 AM317 IO_L4N_VREF_7 AL317 IO_L5P_7 AP247 IO_L5N_7 AR247 IO_L6P_7 AP327 IO_L6N_7 AN327 IO_L7P_7 AN307 IO_L7N_7 AP317 IO_L8P_CC_LC_7 AK297 IO_L8N_CC_LC_7 AJ297 IO_L9P_CC_LC_7 AT247 IO_L9N_CC_LC_7 AT257 IO_L10P_7 AW347 IO_L10N_7 AV347 IO_L11P_7 AW307 IO_L11N_7 AW317 IO_L12P_7 AV337 IO_L12N_VREF_7 AU337 IO_L13P_7 AP257 IO_L13N_7 AP267 IO_L14P_7 AT317 IO_L14N_7 AT307 IO_L15P_7 AU257 IO_L15N_7 AV257 IO_L16P_7 AR317 IO_L16N_7 AR32166 www.xilinx.com Virtex-4 FPGA Packaging and Pinout SpecificationUG075 (v3.3) September 19, 2008

RFF1513 Flip-Chip Fine-Pitch BGA PackageTable 2-7: FF1513 Package — LX100, LX160, and LX200 Devices (Continued)Bank Pin Description Pin Number8 IO_L25P_CC_LC_8 AW128 IO_L25N_CC_LC_8 AV128 IO_L26P_8 AW98 IO_L26N_8 AV98 IO_L27P_8 AN148 IO_L27N_8 AM138 IO_L28P_8 AT118 IO_L28N_VREF_8 AR118 IO_L29P_8 AT138 IO_L29N_8 AR138 IO_L30P_8 AV108 IO_L30N_8 AU108 IO_L31P_8 AW148 IO_L31N_8 AV148 IO_L32P_8 AW118 IO_L32N_8 AW108 IO_L17P_8 AL148 IO_L17N_8 AL138 IO_L18P_8 AU88 IO_L18N_8 AT88 IO_L19P_8 AR128 IO_L19N_8 AP128 IO_L20P_8 AR98 IO_L20N_VREF_8 AP98 IO_L21P_8 AV138 IO_L21N_8 AU138 IO_L22P_8 AT108 IO_L22N_8 AT98 IO_L23P_VRN_8 AU128 IO_L23N_VRP_8 AU118 IO_L24P_CC_LC_8 AV88 IO_L24N_CC_LC_8 AV78 IO_L1P_8 AV58 IO_L1N_8 AU58 IO_L2P_8 AJ108 IO_L2N_8 AJ98 IO_L3P_8 AN9Virtex-4 FPGA Packaging and Pinout Specification www.xilinx.com 167UG075 (v3.3) September 19, 2008

Chapter 2: Pinout TablesRTable 2-7: FF1513 Package — LX100, LX160, and LX200 Devices (Continued)Bank Pin Description Pin Number8 IO_L3N_8 AN88 IO_L4P_8 AL98 IO_L4N_VREF_8 AK98 IO_L5P_8 AM158 IO_L5N_8 AN158 IO_L6P_8 AP78 IO_L6N_8 AN78 IO_L7P_8 AR88 IO_L7N_8 AR78 IO_L8P_CC_LC_8 AV48 IO_L8N_CC_LC_8 AV38 IO_L9P_CC_LC_8 AL118 IO_L9N_CC_LC_8 AK118 IO_L10P_8 AW58 IO_L10N_8 AW48 IO_L11P_8 AW78 IO_L11N_8 AW68 IO_L12P_8 AM108 IO_L12N_VREF_8 AL108 IO_L13P_8 AM118 IO_L13N_8 AN108 IO_L14P_8 AH138 IO_L14N_8 AJ128 IO_L15P_8 AN128 IO_L15N_8 AP118 IO_L16P_8 AU78 IO_L16N_8 AU69 IO_L17P_9 K339 IO_L17N_9 L339 IO_L18P_9 H379 IO_L18N_9 H389 IO_L19P_9 N309 IO_L19N_9 P299 IO_L20P_9 L349 IO_L20N_VREF_9 L359 IO_L21P_9 J369 IO_L21N_9 J37168 www.xilinx.com Virtex-4 FPGA Packaging and Pinout SpecificationUG075 (v3.3) September 19, 2008

RFF1513 Flip-Chip Fine-Pitch BGA PackageTable 2-7: FF1513 Package — LX100, LX160, and LX200 Devices (Continued)Bank Pin Description Pin Number9 IO_L22P_9 K369 IO_L22N_9 L369 IO_L23P_VRN_9 H399 IO_L23N_VRP_9 J399 IO_L24P_CC_LC_9 M339 IO_L24N_CC_LC_9 N329 IO_L1P_9 D349 IO_L1N_9 D359 IO_L2P_9 C379 IO_L2N_9 C389 IO_L3P_9 E349 IO_L3N_9 F349 IO_L4P_9 F359 IO_L4N_VREF_9 G359 IO_L5P_9 D369 IO_L5N_9 D379 IO_L6P_9 H339 IO_L6N_9 H349 IO_L7P_9 E369 IO_L7N_9 F369 IO_L8P_CC_LC_9 C399 IO_L8N_CC_LC_9 D399 IO_L9P_CC_LC_9 J329 IO_L9N_CC_LC_9 K329 IO_L10P_9 G369 IO_L10N_9 G379 IO_L11P_9 E379 IO_L11N_9 E389 IO_L12P_9 H359 IO_L12N_VREF_9 J359 IO_L13P_9 M309 IO_L13N_9 M319 IO_L14P_9 E399 IO_L14N_9 F399 IO_L15P_9 J349 IO_L15N_9 K349 IO_L16P_9 F389 IO_L16N_9 G38Virtex-4 FPGA Packaging and Pinout Specification www.xilinx.com 169UG075 (v3.3) September 19, 2008

Chapter 2: Pinout TablesRTable 2-7: FF1513 Package — LX100, LX160, and LX200 Devices (Continued)Bank Pin Description Pin Number9 IO_L25P_CC_LC_9 R289 IO_L25N_CC_LC_9 R299 IO_L26P_9 M359 IO_L26N_9 N359 IO_L27P_9 K379 IO_L27N_9 K389 IO_L28P_9 N339 IO_L28N_VREF_9 N349 IO_L29P_9 P319 IO_L29N_9 P329 IO_L30P_9 K399 IO_L30N_9 L399 IO_L31P_9 L389 IO_L31N_9 M389 IO_L32P_9 M369 IO_L32N_9 M3710 IO_L17P_10 R1410 IO_L17N_10 T1410 IO_L18P_10 E210 IO_L18N_10 E110 IO_L19P_10 P1210 IO_L19N_10 R1210 IO_L20P_10 K710 IO_L20N_VREF_10 L810 IO_L21P_10 H510 IO_L21N_10 J510 IO_L22P_10 G310 IO_L22N_10 G210 IO_L23P_VRN_10 J610 IO_L23N_VRP_10 K610 IO_L24P_CC_LC_10 F110 IO_L24N_CC_LC_10 G110 IO_L1P_10 A510 IO_L1N_10 A410 IO_L2P_10 A310 IO_L2N_10 B310 IO_L3P_10 B5170 www.xilinx.com Virtex-4 FPGA Packaging and Pinout SpecificationUG075 (v3.3) September 19, 2008

RFF1513 Flip-Chip Fine-Pitch BGA PackageTable 2-7: FF1513 Package — LX100, LX160, and LX200 Devices (Continued)Bank Pin Description Pin Number10 IO_L3N_10 C510 IO_L4P_10 C410 IO_L4N_VREF_10 D410 IO_L5P_10 D610 IO_L5N_10 D510 IO_L6P_10 C310 IO_L6N_10 C210 IO_L7P_10 E610 IO_L7N_10 F610 IO_L8P_CC_LC_10 H710 IO_L8N_CC_LC_10 J710 IO_L9P_CC_LC_10 G710 IO_L9N_CC_LC_10 G610 IO_L10P_10 F510 IO_L10N_10 G510 IO_L11P_10 M1110 IO_L11N_10 N1210 IO_L12P_10 F410 IO_L12N_VREF_10 F310 IO_L13P_10 R1610 IO_L13N_10 T1510 IO_L14P_10 M1010 IO_L14N_10 N1010 IO_L15P_10 E410 IO_L15N_10 E310 IO_L16P_10 D210 IO_L16N_10 D110 IO_L25P_CC_LC_10 P1110 IO_L25N_CC_LC_10 R1110 IO_L26P_10 T1310 IO_L26N_10 U1310 IO_L27P_10 M810 IO_L27N_10 M710 IO_L28P_10 P910 IO_L28N_VREF_10 N810 IO_L29P_10 L610 IO_L29N_10 M610 IO_L30P_10 N7Virtex-4 FPGA Packaging and Pinout Specification www.xilinx.com 171UG075 (v3.3) September 19, 2008

Chapter 2: Pinout TablesRTable 2-7: FF1513 Package — LX100, LX160, and LX200 Devices (Continued)Bank Pin Description Pin Number10 IO_L30N_10 P710 IO_L31P_10 R910 IO_L31N_10 R810 IO_L32P_10 U1210 IO_L32N_10 T1111 IO_L17P_11 AR3711 IO_L17N_11 AR3811 IO_L18P_11 AM3511 IO_L18N_11 AL3511 IO_L19P_11 AP3511 IO_L19N_11 AN3511 IO_L20P_11 AT3911 IO_L20N_VREF_11 AR3911 IO_L21P_11 AG2811 IO_L21N_11 AH2911 IO_L22P_11 AP3611 IO_L22N_11 AP3711 IO_L23P_VRN_11 AN3311 IO_L23N_VRP_11 AN3411 IO_L24P_CC_LC_11 AU3811 IO_L24N_CC_LC_11 AT3811 IO_L1P_11 AG3311 IO_L1N_11 AF3311 IO_L2P_11 AC2811 IO_L2N_11 AD2911 IO_L3P_11 AD2711 IO_L3N_11 AC2711 IO_L4P_11 AE3111 IO_L4N_VREF_11 AE3211 IO_L5P_11 AD2611 IO_L5N_11 AE2611 IO_L6P_11 AF3111 IO_L6N_11 AG3211 IO_L7P_11 AH3211 IO_L7N_11 AH3311 IO_L8P_CC_LC_11 AJ3411 IO_L8N_CC_LC_11 AH34172 www.xilinx.com Virtex-4 FPGA Packaging and Pinout SpecificationUG075 (v3.3) September 19, 2008

RFF1513 Flip-Chip Fine-Pitch BGA PackageTable 2-7: FF1513 Package — LX100, LX160, and LX200 Devices (Continued)Bank Pin Description Pin Number11 IO_L9P_CC_LC_11 AD2511 IO_L9N_CC_LC_11 AE2411 IO_L10P_11 AE2811 IO_L10N_11 AE2911 IO_L11P_11 AL3411 IO_L11N_11 AK3411 IO_L12P_11 AP3911 IO_L12N_VREF_11 AN3911 IO_L13P_11 AF2811 IO_L13N_11 AF2911 IO_L14P_11 AN3711 IO_L14N_11 AN3811 IO_L15P_11 AH3011 IO_L15N_11 AG3011 IO_L16P_11 AK3311 IO_L16N_11 AJ3211 IO_L25P_CC_LC_11 AU3511 IO_L25N_CC_LC_11 AU3611 IO_L26P_11 AM3311 IO_L26N_11 AL3311 IO_L27P_11 AT3411 IO_L27N_11 AT3511 IO_L28P_11 AT3611 IO_L28N_VREF_11 AR3611 IO_L29P_11 AW3611 IO_L29N_11 AW3711 IO_L30P_11 AV3711 IO_L30N_11 AU3711 IO_L31P_11 AW3511 IO_L31N_11 AV3511 IO_L32P_11 AR3411 IO_L32N_11 AP3412 IO_L17P_12 AL612 IO_L17N_12 AK612 IO_L18P_12 AN312 IO_L18N_12 AN212 IO_L19P_12 AH10Virtex-4 FPGA Packaging and Pinout Specification www.xilinx.com 173UG075 (v3.3) September 19, 2008

Chapter 2: Pinout TablesRTable 2-7: FF1513 Package — LX100, LX160, and LX200 Devices (Continued)Bank Pin Description Pin Number12 IO_L19N_12 AH912 IO_L20P_12 AK712 IO_L20N_VREF_12 AJ712 IO_L21P_12 AN512 IO_L21N_12 AN412 IO_L22P_12 AM512 IO_L22N_12 AL512 IO_L23P_VRN_12 AL812 IO_L23N_VRP_12 AK812 IO_L24P_CC_LC_12 AT112 IO_L24N_CC_LC_12 AR112 IO_L1P_12 AH512 IO_L1N_12 AG512 IO_L2P_12 AH312 IO_L2N_12 AH212 IO_L3P_12 AG712 IO_L3N_12 AG612 IO_L4P_12 AJ212 IO_L4N_VREF_12 AJ112 IO_L5P_12 AL112 IO_L5N_12 AK112 IO_L6P_12 AF912 IO_L6N_12 AF812 IO_L7P_12 AG812 IO_L7N_12 AH712 IO_L8P_CC_LC_12 AJ412 IO_L8N_CC_LC_12 AH412 IO_L9P_CC_LC_12 AJ612 IO_L9N_CC_LC_12 AJ512 IO_L10P_12 AK312 IO_L10N_12 AK212 IO_L11P_12 AF1112 IO_L11N_12 AG1012 IO_L12P_12 AE1212 IO_L12N_VREF_12 AE1112 IO_L13P_12 AM312 IO_L13N_12 AL312 IO_L14P_12 AM2174 www.xilinx.com Virtex-4 FPGA Packaging and Pinout SpecificationUG075 (v3.3) September 19, 2008

RFF1513 Flip-Chip Fine-Pitch BGA PackageTable 2-7: FF1513 Package — LX100, LX160, and LX200 Devices (Continued)Bank Pin Description Pin Number12 IO_L14N_12 AM112 IO_L15P_12 AP212 IO_L15N_12 AP112 IO_L16P_12 AL412 IO_L16N_12 AK412 IO_L25P_CC_LC_12 AU212 IO_L25N_CC_LC_12 AU112 IO_L26P_12 AR312 IO_L26N_12 AR212 IO_L27P_12 AT412 IO_L27N_12 AR412 IO_L28P_12 AM712 IO_L28N_VREF_12 AM612 IO_L29P_12 AR612 IO_L29N_12 AP612 IO_L30P_12 AP512 IO_L30N_12 AP412 IO_L31P_12 AT612 IO_L31N_12 AT512 IO_L32P_12 AU312 IO_L32N_12 AT313 IO_L17P_13 T3813 IO_L17N_13 U3813 IO_L18P_13 V2913 IO_L18N_13 V3013 IO_L19P_13 U3613 IO_L19N_13 U3713 IO_L20P_13 V3213 IO_L20N_VREF_13 W3213 IO_L21P_13 W2613 IO_L21N_13 W2713 IO_L22P_13 V3413 IO_L22N_13 V3513 IO_L23P_VRN_13 V3713 IO_L23N_VRP_13 V3813 IO_L24P_CC_LC_13 V3913 IO_L24N_CC_LC_13 W39Virtex-4 FPGA Packaging and Pinout Specification www.xilinx.com 175UG075 (v3.3) September 19, 2008

Chapter 2: Pinout TablesRTable 2-7: FF1513 Package — LX100, LX160, and LX200 Devices (Continued)Bank Pin Description Pin Number13 IO_L1P_13 R3113 IO_L1N_13 R3213 IO_L2P_13 P3413 IO_L2N_13 P3513 IO_L3P_13 T2913 IO_L3N_13 U2813 IO_L4P_13 P3613 IO_L4N_VREF_13 P3713 IO_L5P_13 N3713 IO_L5N_13 N3813 IO_L6P_13 N3913 IO_L6N_13 P3913 IO_L7P_13 R3413 IO_L7N_13 T3413 IO_L8P_CC_LC_13 T3113 IO_L8N_CC_LC_13 U3013 IO_L9P_CC_LC_13 R3613 IO_L9N_CC_LC_13 T3613 IO_L10P_13 T3313 IO_L10N_13 U3213 IO_L11P_13 R3713 IO_L11N_13 R3813 IO_L12P_13 R3913 IO_L12N_VREF_13 T3913 IO_L13P_13 V2513 IO_L13N_13 U2613 IO_L14P_13 V2713 IO_L14N_13 U2713 IO_L15P_13 T3513 IO_L15N_13 U3513 IO_L16P_13 U3313 IO_L16N_13 V3313 IO_L25P_CC_LC_13 W3413 IO_L25N_CC_LC_13 W3513 IO_L26P_13 W3613 IO_L26N_13 W3713 IO_L27P_13 Y3713 IO_L27N_13 Y38176 www.xilinx.com Virtex-4 FPGA Packaging and Pinout SpecificationUG075 (v3.3) September 19, 2008

RFF1513 Flip-Chip Fine-Pitch BGA PackageTable 2-7: FF1513 Package — LX100, LX160, and LX200 Devices (Continued)Bank Pin Description Pin Number13 IO_L28P_13 Y3913 IO_L28N_VREF_13 AA3913 IO_L29P_13 AA3613 IO_L29N_13 Y3613 IO_L30P_13 Y3313 IO_L30N_13 Y3413 IO_L31P_13 AB3613 IO_L31N_13 AB3713 IO_L32P_13 AB3813 IO_L32N_13 AA3814 IO_L17P_14 U1014 IO_L17N_14 T914 IO_L18P_14 R414 IO_L18N_14 R314 IO_L19P_14 T614 IO_L19N_14 T514 IO_L20P_14 R214 IO_L20N_VREF_14 R114 IO_L21P_14 T414 IO_L21N_14 T314 IO_L22P_14 U714 IO_L22N_14 U614 IO_L23P_VRN_14 V1014 IO_L23N_VRP_14 V914 IO_L24P_CC_LC_14 U514 IO_L24N_CC_LC_14 V514 IO_L1P_14 H414 IO_L1N_14 J414 IO_L2P_14 K414 IO_L2N_14 K314 IO_L3P_14 H314 IO_L3N_14 H214 IO_L4P_14 J214 IO_L4N_VREF_14 J114 IO_L5P_14 L514 IO_L5N_14 M514 IO_L6P_14 K2Virtex-4 FPGA Packaging and Pinout Specification www.xilinx.com 177UG075 (v3.3) September 19, 2008

Chapter 2: Pinout TablesRTable 2-7: FF1513 Package — LX100, LX160, and LX200 Devices (Continued)Bank Pin Description Pin Number14 IO_L6N_14 K114 IO_L7P_14 L414 IO_L7N_14 L314 IO_L8P_CC_LC_14 M314 IO_L8N_CC_LC_14 M214 IO_L9P_CC_LC_14 N514 IO_L9N_CC_LC_14 N414 IO_L10P_14 L114 IO_L10N_14 M114 IO_L11P_14 P614 IO_L11N_14 R614 IO_L12P_14 P514 IO_L12N_VREF_14 P414 IO_L13P_14 N314 IO_L13N_14 N214 IO_L14P_14 V1314 IO_L14N_14 V1214 IO_L15P_14 T814 IO_L15N_14 U814 IO_L16P_14 P214 IO_L16N_14 P114 IO_L25P_CC_LC_14 T114 IO_L25N_CC_LC_14 U114 IO_L26P_14 U314 IO_L26N_14 U214 IO_L27P_14 V714 IO_L27N_14 W714 IO_L28P_14 W1014 IO_L28N_VREF_14 W914 IO_L29P_14 W614 IO_L29N_14 W514 IO_L30P_14 AA1014 IO_L30N_14 Y914 IO_L31P_14 AA1114 IO_L31N_14 Y1114 IO_L32P_14 Y1314 IO_L32N_14 W12178 www.xilinx.com Virtex-4 FPGA Packaging and Pinout SpecificationUG075 (v3.3) September 19, 2008

RFF1513 Flip-Chip Fine-Pitch BGA PackageTable 2-7: FF1513 Package — LX100, LX160, and LX200 Devices (Continued)Bank Pin Description Pin Number15 IO_L17P_15 AB2715 IO_L17N_15 AB2815 IO_L18P_15 AE3415 IO_L18N_15 AD3415 IO_L19P_15 AD3115 IO_L19N_15 AD3215 IO_L20P_15 AF3615 IO_L20N_VREF_15 AE3615 IO_L21P_15 AJ3915 IO_L21N_15 AH3915 IO_L22P_15 AG3715 IO_L22N_15 AG3815 IO_L23P_VRN_15 AH3715 IO_L23N_VRP_15 AH3815 IO_L24P_CC_LC_15 AF3415 IO_L24N_CC_LC_15 AF3515 IO_L1P_15 Y2715 IO_L1N_15 AA2815 IO_L2P_15 W2915 IO_L2N_15 W3015 IO_L3P_15 AA3415 IO_L3N_15 AA3515 IO_L4P_15 Y2915 IO_L4N_VREF_15 AA3015 IO_L5P_15 AC3815 IO_L5N_15 AC3915 IO_L6P_15 AA3115 IO_L6N_15 Y3115 IO_L7P_15 AC3515 IO_L7N_15 AB3515 IO_L8P_CC_LC_15 AB3315 IO_L8N_CC_LC_15 AA3315 IO_L9P_CC_LC_15 AC3315 IO_L9N_CC_LC_15 AC3415 IO_L10P_15 AD3715 IO_L10N_15 AC3715 IO_L11P_15 AC3215 IO_L11N_15 AB31Virtex-4 FPGA Packaging and Pinout Specification www.xilinx.com 179UG075 (v3.3) September 19, 2008

Chapter 2: Pinout TablesRTable 2-7: FF1513 Package — LX100, LX160, and LX200 Devices (Continued)Bank Pin Description Pin Number15 IO_L12P_15 AE3915 IO_L12N_VREF_15 AD3915 IO_L13P_15 AF3815 IO_L13N_15 AF3915 IO_L14P_15 AD3515 IO_L14N_15 AD3615 IO_L15P_15 AC3015 IO_L15N_15 AB3015 IO_L16P_15 AE3715 IO_L16N_15 AE3815 IO_L25P_CC_LC_15 AJ3615 IO_L25N_CC_LC_15 AJ3715 IO_L26P_15 AG3515 IO_L26N_15 AG3615 IO_L27P_15 AJ3515 IO_L27N_15 AH3515 IO_L28P_15 AK3815 IO_L28N_VREF_15 AK3915 IO_L29P_15 AM3715 IO_L29N_15 AM3815 IO_L30P_15 AL3815 IO_L30N_15 AL3915 IO_L31P_15 AM3615 IO_L31N_15 AL3615 IO_L32P_15 AK3615 IO_L32N_15 AK3716 IO_L17P_16 AC816 IO_L17N_16 AB816 IO_L18P_16 AD216 IO_L18N_16 AD116 IO_L19P_16 AD516 IO_L19N_16 AD416 IO_L20P_16 AB1316 IO_L20N_VREF_16 AC1316 IO_L21P_16 AB1516 IO_L21N_16 AC1416 IO_L22P_16 AC10180 www.xilinx.com Virtex-4 FPGA Packaging and Pinout SpecificationUG075 (v3.3) September 19, 2008

RFF1513 Flip-Chip Fine-Pitch BGA PackageTable 2-7: FF1513 Package — LX100, LX160, and LX200 Devices (Continued)Bank Pin Description Pin Number16 IO_L22N_16 AD916 IO_L23P_VRN_16 AD716 IO_L23N_VRP_16 AC716 IO_L24P_CC_LC_16 AE316 IO_L24N_CC_LC_16 AE216 IO_L1P_16 V416 IO_L1N_16 W416 IO_L2P_16 V316 IO_L2N_16 V216 IO_L3P_16 W216 IO_L3N_16 W116 IO_L4P_16 Y716 IO_L4N_VREF_16 Y616 IO_L5P_16 Y416 IO_L5N_16 AA416 IO_L6P_16 Y316 IO_L6N_16 Y216 IO_L7P_16 AA316 IO_L7N_16 AB316 IO_L8P_CC_LC_16 Y116 IO_L8N_CC_LC_16 AA116 IO_L9P_CC_LC_16 AA1416 IO_L9N_CC_LC_16 AA1316 IO_L10P_16 AA616 IO_L10N_16 AA516 IO_L11P_16 AB616 IO_L11N_16 AB516 IO_L12P_16 AB216 IO_L12N_VREF_16 AB116 IO_L13P_16 AC316 IO_L13N_16 AC216 IO_L14P_16 AB716 IO_L14N_16 AA816 IO_L15P_16 AB1116 IO_L15N_16 AB1016 IO_L16P_16 AC516 IO_L16N_16 AC416 IO_L25P_CC_LC_16 AC12Virtex-4 FPGA Packaging and Pinout Specification www.xilinx.com 181UG075 (v3.3) September 19, 2008

Chapter 2: Pinout TablesRTable 2-7: FF1513 Package — LX100, LX160, and LX200 Devices (Continued)Bank Pin Description Pin Number16 IO_L25N_CC_LC_16 AD1116 IO_L26P_16 AF116 IO_L26N_16 AE116 IO_L27P_16 AF416 IO_L27N_16 AE416 IO_L28P_16 AE616 IO_L28N_VREF_16 AD616 IO_L29P_16 AF616 IO_L29N_16 AF516 IO_L30P_16 AG216 IO_L30N_16 AG116 IO_L31P_16 AE916 IO_L31N_16 AE816 IO_L32P_16 AG316 IO_L32N_16 AF30 VCCO_0 (1) AA170 VCCO_0 (1) W230 VCCO_0 (1) Y201 VCCO_1 A171 VCCO_1 B241 VCCO_1 C211 VCCO_1 D181 VCCO_1 E251 VCCO_1 F221 VCCO_1 G191 VCCO_1 H161 VCCO_1 J231 VCCO_1 L171 VCCO_1 M241 VCCO_1 P181 VCCO_1 T221 VCCO_1 U192 VCCO_2 AC212 VCCO_2 AD182 VCCO_2 AF222 VCCO_2 AH162 VCCO_2 AJ23182 www.xilinx.com Virtex-4 FPGA Packaging and Pinout SpecificationUG075 (v3.3) September 19, 2008

RFF1513 Flip-Chip Fine-Pitch BGA PackageTable 2-7: FF1513 Package — LX100, LX160, and LX200 Devices (Continued)Bank Pin Description Pin Number2 VCCO_2 AL172 VCCO_2 AM242 VCCO_2 AN212 VCCO_2 AP182 VCCO_2 AR152 VCCO_2 AT222 VCCO_2 AU192 VCCO_2 AV162 VCCO_2 AW233 VCCO_3 K203 VCCO_3 N214 VCCO_4 AG194 VCCO_4 AK205 VCCO_5 A275 VCCO_5 A375 VCCO_5 B345 VCCO_5 C315 VCCO_5 D285 VCCO_5 F325 VCCO_5 G295 VCCO_5 H265 VCCO_5 K305 VCCO_5 L276 VCCO_6 A76 VCCO_6 B146 VCCO_6 C116 VCCO_6 D86 VCCO_6 E156 VCCO_6 F126 VCCO_6 G96 VCCO_6 J136 VCCO_6 K107 VCCO_7 AK307 VCCO_7 AL277 VCCO_7 AN317 VCCO_7 AP287 VCCO_7 AR257 VCCO_7 AT32Virtex-4 FPGA Packaging and Pinout Specification www.xilinx.com 183UG075 (v3.3) September 19, 2008

Chapter 2: Pinout TablesRTable 2-7: FF1513 Package — LX100, LX160, and LX200 Devices (Continued)Bank Pin Description Pin Number7 VCCO_7 AU297 VCCO_7 AV267 VCCO_7 AW338 VCCO_8 AJ138 VCCO_8 AK108 VCCO_8 AM148 VCCO_8 AN118 VCCO_8 AP88 VCCO_8 AT128 VCCO_8 AU98 VCCO_8 AV68 VCCO_8 AW138 VCCO_8 AW39 VCCO_9 D389 VCCO_9 E359 VCCO_9 G399 VCCO_9 H369 VCCO_9 J339 VCCO_9 L379 VCCO_9 M349 VCCO_9 N319 VCCO_9 P2810 VCCO_10 B410 VCCO_10 C110 VCCO_10 E510 VCCO_10 F210 VCCO_10 H610 VCCO_10 L710 VCCO_10 N1110 VCCO_10 P810 VCCO_10 R1510 VCCO_10 T1211 VCCO_11 AD2811 VCCO_11 AE2511 VCCO_11 AF3211 VCCO_11 AG2911 VCCO_11 AJ3311 VCCO_11 AM34184 www.xilinx.com Virtex-4 FPGA Packaging and Pinout SpecificationUG075 (v3.3) September 19, 2008

RFF1513 Flip-Chip Fine-Pitch BGA PackageTable 2-7: FF1513 Package — LX100, LX160, and LX200 Devices (Continued)Bank Pin Description Pin Number11 VCCO_11 AP3811 VCCO_11 AR3511 VCCO_11 AU3911 VCCO_11 AV3612 VCCO_12 AF1212 VCCO_12 AG912 VCCO_12 AH612 VCCO_12 AJ312 VCCO_12 AL712 VCCO_12 AM412 VCCO_12 AN112 VCCO_12 AR512 VCCO_12 AT213 VCCO_13 AA3713 VCCO_13 P3813 VCCO_13 R3513 VCCO_13 T3213 VCCO_13 U2913 VCCO_13 U3913 VCCO_13 V2613 VCCO_13 V3613 VCCO_13 W3314 VCCO_14 J314 VCCO_14 M414 VCCO_14 N114 VCCO_14 R514 VCCO_14 T214 VCCO_14 U914 VCCO_14 V614 VCCO_14 W1314 VCCO_14 Y1015 VCCO_15 AA2715 VCCO_15 AB3415 VCCO_15 AC3115 VCCO_15 AD3815 VCCO_15 AE3515 VCCO_15 AG3915 VCCO_15 AH36Virtex-4 FPGA Packaging and Pinout Specification www.xilinx.com 185UG075 (v3.3) September 19, 2008

Chapter 2: Pinout TablesRTable 2-7: FF1513 Package — LX100, LX160, and LX200 Devices (Continued)Bank Pin Description Pin Number15 VCCO_15 AL3715 VCCO_15 Y3016 VCCO_16 AA716 VCCO_16 AB1416 VCCO_16 AB416 VCCO_16 AC116 VCCO_16 AC1116 VCCO_16 AD816 VCCO_16 AE516 VCCO_16 AF216 VCCO_16 W3N/A VREFN_SM (2) AV19N/A VREFP_SM (2) AV20N/A AVDD_SM (3) AW21N/A VN_SM (2) AW19N/A VP_SM (2) AW20N/A AVSS_SM (2) AV18N/A VREFN_ADC (2) B20N/A VREFP_ADC (2) B21N/A AVDD_ADC (3) B22N/A VN_ADC (2) A20N/A VP_ADC (2) A21N/A AVSS_ADC (2) A19N/A GND B1N/A GND H1N/A GND V1N/A GND AH1N/A GND AV1N/A GND A2N/A GND L2N/A GND AA2N/A GND AL2N/A GND AW2N/A GND D3N/A GND P3186 www.xilinx.com Virtex-4 FPGA Packaging and Pinout SpecificationUG075 (v3.3) September 19, 2008

RFF1513 Flip-Chip Fine-Pitch BGA PackageTable 2-7: FF1513 Package — LX100, LX160, and LX200 Devices (Continued)Bank Pin Description Pin NumberN/A GND AD3N/A GND AP3N/A GND G4N/A GND U4N/A GND AG4N/A GND AU4N/A GND K5N/A GND Y5N/A GND AK5N/A GND C6N/A GND N6N/A GND AC6N/A GND AN6N/A GND F7N/A GND T7N/A GND AF7N/A GND AT7N/A GND J8N/A GND W8N/A GND AJ8N/A GND AW8N/A GND B9N/A GND M9N/A GND AB9N/A GND AM9N/A GND E10N/A GND R10N/A GND AE10N/A GND AR10N/A GND H11N/A GND V11N/A GND AH11N/A GND AV11N/A GND A12N/A GND L12N/A GND AA12N/A GND AG12N/A GND AL12Virtex-4 FPGA Packaging and Pinout Specification www.xilinx.com 187UG075 (v3.3) September 19, 2008

Chapter 2: Pinout TablesRTable 2-7: FF1513 Package — LX100, LX160, and LX200 Devices (Continued)Bank Pin Description Pin NumberN/A GND D13N/A GND K13N/A GND M13N/A GND P13N/A GND AD13N/A GND AF13N/A GND AK13N/A GND AP13N/A GND G14N/A GND L14N/A GND N14N/A GND U14N/A GND W14N/A GND AE14N/A GND AG14N/A GND AJ14N/A GND AU14N/A GND K15N/A GND M15N/A GND P15N/A GND V15N/A GND Y15N/A GND AD15N/A GND AF15N/A GND AK15N/A GND C16N/A GND N16N/A GND U16N/A GND W16N/A GND AC16N/A GND AE16N/A GND AN16N/A GND F17N/A GND T17N/A GND V17N/A GND AF17N/A GND AT17N/A GND J18188 www.xilinx.com Virtex-4 FPGA Packaging and Pinout SpecificationUG075 (v3.3) September 19, 2008

RFF1513 Flip-Chip Fine-Pitch BGA PackageTable 2-7: FF1513 Package — LX100, LX160, and LX200 Devices (Continued)Bank Pin Description Pin NumberN/A GND W18N/A GND AC18N/A GND AJ18N/A GND AW18N/A GND B19N/A GND M19N/A GND V19N/A GND AB19N/A GND AD19N/A GND AM19N/A GND E20N/A GND R20N/A GND AE20N/A GND AR20N/A GND H21N/A GND T21N/A GND V21N/A GND AB21N/A GND AH21N/A GND AV21N/A GND A22N/A GND L22N/A GND U22N/A GND AA22N/A GND AL22N/A GND D23N/A GND P23N/A GND AB23N/A GND AD23N/A GND AP23N/A GND G24N/A GND R24N/A GND U24N/A GND AA24N/A GND AC24N/A GND AG24N/A GND AU24N/A GND K25Virtex-4 FPGA Packaging and Pinout Specification www.xilinx.com 189UG075 (v3.3) September 19, 2008

Chapter 2: Pinout TablesRTable 2-7: FF1513 Package — LX100, LX160, and LX200 Devices (Continued)Bank Pin Description Pin NumberN/A GND P25N/A GND T25N/A GND Y25N/A GND AB25N/A GND AF25N/A GND AH25N/A GND AK25N/A GND C26N/A GND L26N/A GND N26N/A GND R26N/A GND AA26N/A GND AC26N/A GND AG26N/A GND AJ26N/A GND AN26N/A GND F27N/A GND K27N/A GND P27N/A GND T27N/A GND AF27N/A GND AH27N/A GND AK27N/A GND AT27N/A GND J28N/A GND N28N/A GND W28N/A GND AJ28N/A GND AW28N/A GND B29N/A GND M29N/A GND AB29N/A GND AM29N/A GND E30N/A GND R30N/A GND AE30N/A GND AR30N/A GND H31190 www.xilinx.com Virtex-4 FPGA Packaging and Pinout SpecificationUG075 (v3.3) September 19, 2008

RFF1513 Flip-Chip Fine-Pitch BGA PackageTable 2-7: FF1513 Package — LX100, LX160, and LX200 Devices (Continued)Bank Pin Description Pin NumberN/A GND V31N/A GND AH31N/A GND AV31N/A GND A32N/A GND L32N/A GND AA32N/A GND AL32N/A GND D33N/A GND P33N/A GND AD33N/A GND AP33N/A GND G34N/A GND U34N/A GND AG34N/A GND AU34N/A GND K35N/A GND Y35N/A GND AK35N/A GND C36N/A GND N36N/A GND AC36N/A GND AN36N/A GND F37N/A GND T37N/A GND AF37N/A GND AT37N/A GND A38N/A GND J38N/A GND W38N/A GND AJ38N/A GND AW38N/A GND B39N/A GND M39N/A GND AB39N/A GND AM39N/A GND AV39N/A VCCAUX H8Virtex-4 FPGA Packaging and Pinout Specification www.xilinx.com 191UG075 (v3.3) September 19, 2008

Chapter 2: Pinout TablesRTable 2-7: FF1513 Package — LX100, LX160, and LX200 Devices (Continued)Bank Pin Description Pin NumberN/A VCCAUX Y8N/A VCCAUX L9N/A VCCAUX AC9N/A VCCAUX P10N/A VCCAUX AF10N/A VCCAUX U11N/A VCCAUX AJ11N/A VCCAUX K12N/A VCCAUX Y12N/A VCCAUX AM12N/A VCCAUX J15N/A VCCAUX AL15N/A VCCAUX H18N/A VCCAUX AK18N/A VCCAUX AA19N/A VCCAUX AN19N/A VCCAUX G21N/A VCCAUX W21N/A VCCAUX K22N/A VCCAUX AM22N/A VCCAUX J25N/A VCCAUX AL25N/A VCCAUX H28N/A VCCAUX Y28N/A VCCAUX AK28N/A VCCAUX L29N/A VCCAUX AC29N/A VCCAUX P30N/A VCCAUX AF30N/A VCCAUX U31N/A VCCAUX AJ31N/A VCCAUX Y32N/A VCCAUX AM32N/A VCCINT R7N/A VCCINT AE7N/A VCCINT K8N/A VCCINT V8N/A VCCINT AH8192 www.xilinx.com Virtex-4 FPGA Packaging and Pinout SpecificationUG075 (v3.3) September 19, 2008

RFF1513 Flip-Chip Fine-Pitch BGA PackageTable 2-7: FF1513 Package — LX100, LX160, and LX200 Devices (Continued)Bank Pin Description Pin NumberN/A VCCINT AM8N/A VCCINT N9N/A VCCINT AA9N/A VCCINT F10N/A VCCINT T10N/A VCCINT AD10N/A VCCINT AP10N/A VCCINT J11N/A VCCINT W11N/A VCCINT AG11N/A VCCINT M12N/A VCCINT AB12N/A VCCINT AD12N/A VCCINT AH12N/A VCCINT AK12N/A VCCINT L13N/A VCCINT N13N/A VCCINT R13N/A VCCINT AE13N/A VCCINT AG13N/A VCCINT AN13N/A VCCINT H14N/A VCCINT K14N/A VCCINT M14N/A VCCINT P14N/A VCCINT V14N/A VCCINT Y14N/A VCCINT AD14N/A VCCINT AF14N/A VCCINT AH14N/A VCCINT AK14N/A VCCINT L15N/A VCCINT N15N/A VCCINT U15N/A VCCINT W15N/A VCCINT AA15N/A VCCINT AC15N/A VCCINT AE15Virtex-4 FPGA Packaging and Pinout Specification www.xilinx.com 193UG075 (v3.3) September 19, 2008

Chapter 2: Pinout TablesRTable 2-7: FF1513 Package — LX100, LX160, and LX200 Devices (Continued)Bank Pin Description Pin NumberN/A VCCINT AG15N/A VCCINT AJ15N/A VCCINT M16N/A VCCINT P16N/A VCCINT T16N/A VCCINT V16N/A VCCINT AD16N/A VCCINT AF16N/A VCCINT AM16N/A VCCINT G17N/A VCCINT U17N/A VCCINT W17N/A VCCINT AC17N/A VCCINT AE17N/A VCCINT AJ17N/A VCCINT AR17N/A VCCINT K18N/A VCCINT V18N/A VCCINT AB18N/A VCCINT N19N/A VCCINT R19N/A VCCINT W19N/A VCCINT AC19N/A VCCINT AE19N/A VCCINT F20N/A VCCINT V20N/A VCCINT AB20N/A VCCINT AD20N/A VCCINT AP20N/A VCCINT R21N/A VCCINT U21N/A VCCINT AA21N/A VCCINT AE21N/A VCCINT AG21N/A VCCINT V22N/A VCCINT AB22N/A VCCINT AD22N/A VCCINT AK22194 www.xilinx.com Virtex-4 FPGA Packaging and Pinout SpecificationUG075 (v3.3) September 19, 2008

RFF1513 Flip-Chip Fine-Pitch BGA PackageTable 2-7: FF1513 Package — LX100, LX160, and LX200 Devices (Continued)Bank Pin Description Pin NumberN/A VCCINT E23N/A VCCINT L23N/A VCCINT R23N/A VCCINT U23N/A VCCINT AA23N/A VCCINT AC23N/A VCCINT AN23N/A VCCINT H24N/A VCCINT P24N/A VCCINT T24N/A VCCINT AB24N/A VCCINT AD24N/A VCCINT AF24N/A VCCINT AH24N/A VCCINT L25N/A VCCINT N25N/A VCCINT R25N/A VCCINT U25N/A VCCINT W25N/A VCCINT AA25N/A VCCINT AC25N/A VCCINT AG25N/A VCCINT AJ25N/A VCCINT K26N/A VCCINT M26N/A VCCINT P26N/A VCCINT T26N/A VCCINT Y26N/A VCCINT AB26N/A VCCINT AF26N/A VCCINT AH26N/A VCCINT AK26N/A VCCINT AM26N/A VCCINT G27N/A VCCINT N27N/A VCCINT R27N/A VCCINT AE27N/A VCCINT AG27Virtex-4 FPGA Packaging and Pinout Specification www.xilinx.com 195UG075 (v3.3) September 19, 2008

Chapter 2: Pinout TablesRTable 2-7: FF1513 Package — LX100, LX160, and LX200 Devices (Continued)Bank Pin Description Pin NumberN/A VCCINT AJ27N/A VCCINT K28N/A VCCINT M28N/A VCCINT T28N/A VCCINT V28N/A VCCINT AH28N/A VCCINT N29N/A VCCINT AA29N/A VCCINT AL29N/A VCCINT F30N/A VCCINT T30N/A VCCINT AD30N/A VCCINT AP30N/A VCCINT W31N/A VCCINT AG31N/A VCCINT H32N/A VCCINT M32N/A VCCINT AB32N/A VCCINT AK32N/A VCCINT R33N/A VCCINT AE33Notes:1. This voltage is also referred to as V CC_CONFIG in the Virtex-4 Configuration Guide.2. Connect this reserved pin to GND.3. Connect this reserved pin to 2.5V (sharing the same PCB supply distribution as V CCAUX is acceptable).196 www.xilinx.com Virtex-4 FPGA Packaging and Pinout SpecificationUG075 (v3.3) September 19, 2008

RFF1517 Flip-Chip Fine-Pitch BGA PackageFF1517 Flip-Chip Fine-Pitch BGA PackageAs shown in Table 2-8, Virtex-4 XC4VFX140 and XC4VFX100 devices are available in theFF1517 flip-chip fine-pitch BGA package.The “No Connect” column in Table 2-8 shows pins that are not available in FX100 devices.To be assured of having the very latest Virtex-4 FPGA pinout information, visitwww.xilinx.com and check for any updates to this document. ASCII package pinout filesare also available for download from the Xilinx website.Table 2-8: FF1517 Package — FX140 and FX100 DevicesBank Pin Description Pin Number0 HSWAPEN_0 V230 CCLK_0 W200 D_IN_0 Y160 PROG_B_0 W220 INIT_B_0 V240 CS_B_0 Y170 DONE_0 Y190 RDWR_B_0 Y180 VBATT_0 W240 M2_0 Y220 PWRDWN_B_0 Y210 TMS_0 AA160 M0_0 Y230 TDO_0 AB160 TCK_0 AA180 M1_0 Y240 DOUT_BUSY_0 AA200 TDI_0 AB170 TDN_0 E180 TDP_0 E19No Connects inFX100 Devices1 IO_L1P_D31_LC_1 L241 IO_L1N_D30_LC_1 K231 IO_L2P_D29_LC_1 D171 IO_L2N_D28_LC_1 E171 IO_L3P_D27_LC_1 K241 IO_L3N_D26_LC_1 J241 IO_L4P_D25_LC_1 L161 IO_L4N_D24_VREF_LC_1 M16Virtex-4 FPGA Packaging and Pinout Specification www.xilinx.com 197UG075 (v3.3) September 19, 2008

Chapter 2: Pinout TablesRTable 2-8: FF1517 Package — FX140 and FX100 Devices (Continued)Bank Pin Description Pin Number1 IO_L5P_D23_LC_1 H241 IO_L5N_D22_LC_1 H231 IO_L6P_D21_LC_1 J161 IO_L6N_D20_LC_1 K161 IO_L7P_D19_LC_1 M251 IO_L7N_D18_LC_1 N241 IO_L8P_D17_CC_LC_1 G151 IO_L8N_D16_CC_LC_1 H151 IO_L9P_GC_LC_1 M211 IO_L9N_GC_LC_1 N201 IO_L10P_GC_LC_1 N191 IO_L10N_GC_LC_1 P191 IO_L11P_GC_LC_1 F211 IO_L11N_GC_LC_1 E211 IO_L12P_GC_LC_1 R181 IO_L12N_GC_VREF_LC_1 P171 IO_L13P_GC_LC_1 G221 IO_L13N_GC_LC_1 G211 IO_L14P_GC_LC_1 N181 IO_L14N_GC_LC_1 M171 IO_L15P_GC_LC_1 J221 IO_L15N_GC_LC_1 H221 IO_L16P_GC_CC_LC_1 L181 IO_L16N_GC_CC_LC_1 M181 IO_L17P_CC_LC_1 N231 IO_L17N_CC_LC_1 N221 IO_L18P_VRN_LC_1 K181 IO_L18N_VRP_LC_1 K171 IO_L19P_LC_1 M231 IO_L19N_LC_1 L231 IO_L20P_LC_1 C181 IO_L20N_VREF_LC_1 C171 IO_L21P_LC_1 G231 IO_L21N_LC_1 F231 IO_L22P_LC_1 H171 IO_L22N_LC_1 J171 IO_L23P_LC_1 E23No Connects inFX100 Devices198 www.xilinx.com Virtex-4 FPGA Packaging and Pinout SpecificationUG075 (v3.3) September 19, 2008

RFF1517 Flip-Chip Fine-Pitch BGA PackageTable 2-8: FF1517 Package — FX140 and FX100 Devices (Continued)Bank Pin Description Pin Number1 IO_L23N_LC_1 E221 IO_L24P_LC_1 G171 IO_L24N_LC_1 G16No Connects inFX100 Devices2 IO_L1P_D15_CC_LC_2 AM252 IO_L1N_D14_CC_LC_2 AN252 IO_L2P_D13_LC_2 AL162 IO_L2N_D12_LC_2 AK162 IO_L3P_D11_LC_2 AN242 IO_L3N_D10_LC_2 AM232 IO_L4P_D9_LC_2 AJ162 IO_L4N_D8_VREF_LC_2 AH152 IO_L5P_D7_LC_2 AL242 IO_L5N_D6_LC_2 AL232 IO_L6P_D5_LC_2 AR172 IO_L6N_D4_LC_2 AP172 IO_L7P_D3_LC_2 AJ242 IO_L7N_D2_LC_2 AK242 IO_L8P_D1_LC_2 AM172 IO_L8N_D0_LC_2 AM162 IO_L9P_GC_CC_LC_2 AF232 IO_L9N_GC_CC_LC_2 AE222 IO_L10P_GC_LC_2 AG182 IO_L10N_GC_LC_2 AH172 IO_L11P_GC_LC_2 AR222 IO_L11N_GC_LC_2 AR212 IO_L12P_GC_LC_2 AR192 IO_L12N_GC_VREF_LC_2 AR182 IO_L13P_GC_LC_2 AH222 IO_L13N_GC_LC_2 AG212 IO_L14P_GC_LC_2 AP192 IO_L14N_GC_LC_2 AN192 IO_L15P_GC_LC_2 AG222 IO_L15N_GC_LC_2 AF212 IO_L16P_GC_LC_2 AG202 IO_L16N_GC_LC_2 AH19Virtex-4 FPGA Packaging and Pinout Specification www.xilinx.com 199UG075 (v3.3) September 19, 2008

Chapter 2: Pinout TablesRTable 2-8: FF1517 Package — FX140 and FX100 Devices (Continued)Bank Pin Description Pin Number2 IO_L17P_LC_2 AH242 IO_L17N_LC_2 AH232 IO_L18P_LC_2 AK172 IO_L18N_LC_2 AJ172 IO_L19P_LC_2 AT232 IO_L19N_LC_2 AU232 IO_L20P_LC_2 AG172 IO_L20N_VREF_LC_2 AG162 IO_L21P_LC_2 AN232 IO_L21N_LC_2 AR232 IO_L22P_LC_2 AN182 IO_L22N_LC_2 AN172 IO_L23P_VRN_LC_2 AK232 IO_L23N_VRP_LC_2 AJ222 IO_L24P_CC_LC_2 AM182 IO_L24N_CC_LC_2 AL18No Connects inFX100 Devices3 IO_L1P_GC_CC_LC_3 J203 IO_L1N_GC_CC_LC_3 J193 IO_L2P_GC_VRN_LC_3 K193 IO_L2N_GC_VRP_LC_3 L193 IO_L3P_GC_LC_3 H203 IO_L3N_GC_LC_3 H193 IO_L4P_GC_LC_3 G203 IO_L4N_GC_VREF_LC_3 F203 IO_L5P_GC_LC_3 L213 IO_L5N_GC_LC_3 L203 IO_L6P_GC_LC_3 F193 IO_L6N_GC_LC_3 F183 IO_L7P_GC_LC_3 K213 IO_L7N_GC_LC_3 J213 IO_L8P_GC_LC_3 G183 IO_L8N_GC_LC_3 H184 IO_L1P_GC_LC_4 AP224 IO_L1N_GC_LC_4 AP21200 www.xilinx.com Virtex-4 FPGA Packaging and Pinout SpecificationUG075 (v3.3) September 19, 2008

RFF1517 Flip-Chip Fine-Pitch BGA PackageTable 2-8: FF1517 Package — FX140 and FX100 Devices (Continued)Bank Pin Description Pin Number4 IO_L2P_GC_LC_4 AN204 IO_L2N_GC_LC_4 AP204 IO_L3P_GC_LC_4 AM224 IO_L3N_GC_LC_4 AN224 IO_L4P_GC_LC_4 AL204 IO_L4N_GC_VREF_LC_4 AL194 IO_L5P_GC_LC_4 AK214 IO_L5N_GC_LC_4 AL214 IO_L6P_GC_LC_4 AK194 IO_L6N_GC_LC_4 AJ194 IO_L7P_GC_VRN_LC_4 AJ214 IO_L7N_GC_VRP_LC_4 AJ204 IO_L8P_GC_CC_LC_4 AM214 IO_L8N_GC_CC_LC_4 AM20No Connects inFX100 Devices5 IO_L1P_ADC7_5 C285 IO_L1N_ADC7_5 C275 IO_L2P_ADC6_5 K285 IO_L2N_ADC6_5 L285 IO_L3P_ADC5_5 K295 IO_L3N_ADC5_5 L295 IO_L4P_5 G285 IO_L4N_VREF_5 H285 IO_L5P_ADC4_5 J295 IO_L5N_ADC4_5 H295 IO_L6P_ADC3_5 E285 IO_L6N_ADC3_5 F285 IO_L7P_ADC2_5 E295 IO_L7N_ADC2_5 F295 IO_L8P_CC_ADC1_LC_5 J275 IO_L8N_CC_ADC1_LC_5 K275 IO_L17P_5 G315 IO_L17N_5 F315 IO_L18P_5 D265 IO_L18N_5 E265 IO_L19P_5 E31Virtex-4 FPGA Packaging and Pinout Specification www.xilinx.com 201UG075 (v3.3) September 19, 2008

Chapter 2: Pinout TablesRTable 2-8: FF1517 Package — FX140 and FX100 Devices (Continued)Bank Pin Description Pin Number5 IO_L19N_5 D315 IO_L20P_5 G255 IO_L20N_VREF_5 H255 IO_L21P_5 L315 IO_L21N_5 L305 IO_L22P_5 F255 IO_L22N_5 F245 IO_L23P_VRN_5 K315 IO_L23N_VRP_5 J315 IO_L24P_CC_LC_5 C255 IO_L24N_CC_LC_5 D255 IO_L9P_CC_LC_5 D295 IO_L9N_CC_LC_5 C295 IO_L10P_5 G275 IO_L10N_5 H275 IO_L11P_5 J305 IO_L11N_5 H305 IO_L12P_5 D275 IO_L12N_VREF_5 E275 IO_L13P_5 G305 IO_L13N_5 F305 IO_L14P_5 J265 IO_L14N_5 K265 IO_L15P_5 D305 IO_L15N_5 C305 IO_L16P_5 F265 IO_L16N_5 G265 IO_L25P_CC_LC_5 E325 IO_L25N_CC_LC_5 D325 IO_L26P_5 M285 IO_L26N_5 M275 IO_L27P_5 G335 IO_L27N_5 G325 IO_L28P_5 L265 IO_L28N_VREF_5 M265 IO_L29P_5 F335 IO_L29N_5 E33No Connects inFX100 Devices202 www.xilinx.com Virtex-4 FPGA Packaging and Pinout SpecificationUG075 (v3.3) September 19, 2008

RFF1517 Flip-Chip Fine-Pitch BGA PackageTable 2-8: FF1517 Package — FX140 and FX100 Devices (Continued)Bank Pin Description Pin Number5 IO_L30P_5 D245 IO_L30N_5 E245 IO_L31P_5 C335 IO_L31N_5 C325 IO_L32P_5 C245 IO_L32N_5 C23No Connects inFX100 Devices6 IO_L1P_6 C106 IO_L1N_6 D106 IO_L2P_6 H106 IO_L2N_6 J106 IO_L3P_6 J116 IO_L3N_6 K116 IO_L4P_6 F106 IO_L4N_VREF_6 G106 IO_L5P_6 F116 IO_L5N_6 G116 IO_L6P_6 H96 IO_L6N_6 J96 IO_L7P_6 D116 IO_L7N_6 E116 IO_L8P_CC_LC_6 E96 IO_L8N_CC_LC_6 F96 IO_L17P_6 F136 IO_L17N_6 E136 IO_L18P_6 C86 IO_L18N_6 C76 IO_L19P_6 C136 IO_L19N_6 C126 IO_L20P_6 D76 IO_L20N_VREF_6 E76 IO_L21P_6 J146 IO_L21N_6 H146 IO_L22P_6 F66 IO_L22N_6 F56 IO_L23P_VRN_6 F14Virtex-4 FPGA Packaging and Pinout Specification www.xilinx.com 203UG075 (v3.3) September 19, 2008

Chapter 2: Pinout TablesRTable 2-8: FF1517 Package — FX140 and FX100 Devices (Continued)Bank Pin Description Pin Number6 IO_L23N_VRP_6 E146 IO_L24P_CC_LC_6 D66 IO_L24N_CC_LC_6 E66 IO_L9P_CC_LC_6 K136 IO_L9N_CC_LC_6 J126 IO_L10P_6 K96 IO_L10N_6 L106 IO_L11P_6 H126 IO_L11N_6 G126 IO_L12P_6 C96 IO_L12N_VREF_6 D96 IO_L13P_6 E126 IO_L13N_6 D126 IO_L14P_6 G86 IO_L14N_6 H86 IO_L15P_6 H136 IO_L15N_6 G136 IO_L16P_6 E86 IO_L16N_6 F86 IO_L25P_CC_LC_6 D146 IO_L25N_CC_LC_6 C146 IO_L26P_6 C56 IO_L26N_6 D56 IO_L27P_6 D156 IO_L27N_6 C156 IO_L28P_6 E46 IO_L28N_VREF_6 F46 IO_L29P_6 F166 IO_L29N_6 F156 IO_L30P_6 C46 IO_L30N_6 D46 IO_L31P_6 E166 IO_L31N_6 D166 IO_L32P_6 E36 IO_L32N_6 F3No Connects inFX100 Devices204 www.xilinx.com Virtex-4 FPGA Packaging and Pinout SpecificationUG075 (v3.3) September 19, 2008

RFF1517 Flip-Chip Fine-Pitch BGA PackageTable 2-8: FF1517 Package — FX140 and FX100 Devices (Continued)Bank Pin Description Pin Number7 IO_L25P_CC_SM7_LC_7 AT317 IO_L25N_CC_SM7_LC_7 AU317 IO_L26P_SM6_7 AR297 IO_L26N_SM6_7 AT297 IO_L27P_SM5_7 AP317 IO_L27N_SM5_7 AR317 IO_L28P_7 AN297 IO_L28N_VREF_7 AP297 IO_L29P_SM4_7 AL307 IO_L29N_SM4_7 AM307 IO_L30P_SM3_7 AT307 IO_L30N_SM3_7 AU307 IO_L31P_SM2_7 AN307 IO_L31N_SM2_7 AP307 IO_L32P_SM1_7 AK297 IO_L32N_SM1_7 AL297 IO_L17P_7 AP327 IO_L17N_7 AR327 IO_L18P_7 AU287 IO_L18N_7 AU277 IO_L19P_7 AM327 IO_L19N_7 AN327 IO_L20P_7 AT287 IO_L20N_VREF_7 AR287 IO_L21P_7 AJ307 IO_L21N_7 AK317 IO_L22P_7 AN287 IO_L22N_7 AN277 IO_L23P_VRN_7 AL317 IO_L23N_VRP_7 AM317 IO_L24P_CC_LC_7 AM287 IO_L24N_CC_LC_7 AL287 IO_L1P_7 AP377 IO_L1N_7 AR377 IO_L2P_7 AT247 IO_L2N_7 AR247 IO_L3P_7 AT36No Connects inFX100 DevicesVirtex-4 FPGA Packaging and Pinout Specification www.xilinx.com 205UG075 (v3.3) September 19, 2008

Chapter 2: Pinout TablesRTable 2-8: FF1517 Package — FX140 and FX100 Devices (Continued)Bank Pin Description Pin Number7 IO_L3N_7 AU367 IO_L4P_7 AU257 IO_L4N_VREF_7 AT257 IO_L5P_7 AP367 IO_L5N_7 AR367 IO_L6P_7 AP257 IO_L6N_7 AP247 IO_L7P_7 AP357 IO_L7N_7 AP347 IO_L8P_CC_LC_7 AU267 IO_L8N_CC_LC_7 AT267 IO_L9P_CC_LC_7 AT357 IO_L9N_CC_LC_7 AU357 IO_L10P_7 AR267 IO_L10N_7 AP267 IO_L11P_7 AR347 IO_L11N_7 AT347 IO_L12P_7 AR277 IO_L12N_VREF_7 AP277 IO_L13P_7 AU337 IO_L13N_7 AU327 IO_L14P_7 AM277 IO_L14N_7 AM267 IO_L15P_7 AR337 IO_L15N_7 AT337 IO_L16P_7 AK277 IO_L16N_7 AL26No Connects inFX100 Devices8 IO_L25P_CC_LC_8 AL138 IO_L25N_CC_LC_8 AM138 IO_L26P_8 AP118 IO_L26N_8 AR118 IO_L27P_8 AR148 IO_L27N_8 AR138 IO_L28P_8 AL118 IO_L28N_VREF_8 AM11206 www.xilinx.com Virtex-4 FPGA Packaging and Pinout SpecificationUG075 (v3.3) September 19, 2008

RFF1517 Flip-Chip Fine-Pitch BGA PackageTable 2-8: FF1517 Package — FX140 and FX100 Devices (Continued)Bank Pin Description Pin Number8 IO_L29P_8 AT148 IO_L29N_8 AT138 IO_L30P_8 AP128 IO_L30N_8 AR128 IO_L31P_8 AU138 IO_L31N_8 AU128 IO_L32P_8 AK118 IO_L32N_8 AJ118 IO_L17P_8 AN148 IO_L17N_8 AP148 IO_L18P_8 AP108 IO_L18N_8 AN108 IO_L19P_8 AK138 IO_L19N_8 AK128 IO_L20P_8 AJ108 IO_L20N_VREF_8 AJ98 IO_L21P_8 AJ128 IO_L21N_8 AH128 IO_L22P_8 AM108 IO_L22N_8 AL108 IO_L23P_VRN_8 AN138 IO_L23N_VRP_8 AN128 IO_L24P_CC_LC_8 AT118 IO_L24N_CC_LC_8 AU118 IO_L1P_8 AH148 IO_L1N_8 AH138 IO_L2P_8 AR78 IO_L2N_8 AP78 IO_L3P_8 AT188 IO_L3N_8 AU178 IO_L4P_8 AU88 IO_L4N_VREF_8 AU78 IO_L5P_8 AT168 IO_L5N_8 AU168 IO_L6P_8 AT88 IO_L6N_8 AR88 IO_L7P_8 AP16No Connects inFX100 DevicesVirtex-4 FPGA Packaging and Pinout Specification www.xilinx.com 207UG075 (v3.3) September 19, 2008

Chapter 2: Pinout TablesRTable 2-8: FF1517 Package — FX140 and FX100 Devices (Continued)Bank Pin Description Pin Number8 IO_L7N_8 AR168 IO_L8P_CC_LC_8 AN88 IO_L8N_CC_LC_8 AN78 IO_L9P_CC_LC_8 AT158 IO_L9N_CC_LC_8 AU158 IO_L10P_8 AT98 IO_L10N_8 AR98 IO_L11P_8 AN158 IO_L11N_8 AP158 IO_L12P_8 AP98 IO_L12N_VREF_8 AN98 IO_L13P_8 AM158 IO_L13N_8 AL148 IO_L14P_8 AL98 IO_L14N_8 AK98 IO_L15P_8 AJ148 IO_L15N_8 AK148 IO_L16P_8 AU108 IO_L16N_8 AT10No Connects inFX100 Devices9 IO_L17P_9 N339 IO_L17N_9 M339 IO_L18P_9 H379 IO_L18N_9 G379 IO_L19P_9 R329 IO_L19N_9 P329 IO_L20P_9 P319 IO_L20N_VREF_9 P309 IO_L21P_9 R319 IO_L21N_9 T319 IO_L22P_9 M359 IO_L22N_9 L359 IO_L23P_VRN_9 R339 IO_L23N_VRP_9 T339 IO_L24P_CC_LC_9 N359 IO_L24N_CC_LC_9 N34208 www.xilinx.com Virtex-4 FPGA Packaging and Pinout SpecificationUG075 (v3.3) September 19, 2008

RFF1517 Flip-Chip Fine-Pitch BGA PackageTable 2-8: FF1517 Package — FX140 and FX100 Devices (Continued)Bank Pin Description Pin Number9 IO_L1P_9 K329 IO_L1N_9 J329 IO_L2P_9 D349 IO_L2N_9 C349 IO_L3P_9 G359 IO_L3N_9 F359 IO_L4P_9 D359 IO_L4N_VREF_9 C359 IO_L5P_9 E379 IO_L5N_9 D379 IO_L6P_9 F349 IO_L6N_9 E349 IO_L7P_9 G369 IO_L7N_9 F369 IO_L8P_CC_LC_9 H339 IO_L8N_CC_LC_9 H329 IO_L9P_CC_LC_9 J359 IO_L9N_CC_LC_9 H359 IO_L10P_9 E369 IO_L10N_9 D369 IO_L11P_9 L349 IO_L11N_9 K349 IO_L12P_9 J349 IO_L12N_VREF_9 H349 IO_L13P_9 J379 IO_L13N_9 J369 IO_L14P_9 N309 IO_L14N_9 M319 IO_L15P_9 N329 IO_L15N_9 M329 IO_L16P_9 L339 IO_L16N_9 K339 IO_L25P_CC_LC_9 T309 IO_L25N_CC_LC_9 T299 IO_L26P_9 U339 IO_L26N_9 U329 IO_L27P_9 U31No Connects inFX100 DevicesVirtex-4 FPGA Packaging and Pinout Specification www.xilinx.com 209UG075 (v3.3) September 19, 2008

Chapter 2: Pinout TablesRTable 2-8: FF1517 Package — FX140 and FX100 Devices (Continued)Bank Pin Description Pin Number9 IO_L27N_9 U309 IO_L28P_9 U279 IO_L28N_VREF_9 U269 IO_L29P_9 V289 IO_L29N_9 U289 IO_L30P_9 W269 IO_L30N_9 V259 IO_L31P_9 V309 IO_L31N_9 V299 IO_L32P_9 W279 IO_L32N_9 V27No Connects inFX100 Devices10 IO_L17P_10 L610 IO_L17N_10 M610 IO_L18P_10 M310 IO_L18N_10 N310 IO_L19P_10 K410 IO_L19N_10 L410 IO_L20P_10 N510 IO_L20N_VREF_10 P510 IO_L21P_10 N710 IO_L21N_10 P710 IO_L22P_10 P610 IO_L22N_10 R610 IO_L23P_VRN_10 N410 IO_L23N_VRP_10 P410 IO_L24P_CC_LC_10 R810 IO_L24N_CC_LC_10 R710 IO_L1P_10 N1210 IO_L1N_10 M1110 IO_L2P_10 M1010 IO_L2N_10 N1010 IO_L3P_10 G710 IO_L3N_10 H710 IO_L4P_10 L810 IO_L4N_VREF_10 M7210 www.xilinx.com Virtex-4 FPGA Packaging and Pinout SpecificationUG075 (v3.3) September 19, 2008

RFF1517 Flip-Chip Fine-Pitch BGA PackageTable 2-8: FF1517 Package — FX140 and FX100 Devices (Continued)Bank Pin Description Pin Number10 IO_L5P_10 P1110 IO_L5N_10 R1110 IO_L6P_10 J610 IO_L6N_10 K610 IO_L7P_10 P1210 IO_L7N_10 R1210 IO_L8P_CC_LC_10 G310 IO_L8N_CC_LC_10 H310 IO_L9P_CC_LC_10 G610 IO_L9N_CC_LC_10 G510 IO_L10P_10 P1010 IO_L10N_10 P910 IO_L11P_10 K810 IO_L11N_10 K710 IO_L12P_10 H410 IO_L12N_VREF_10 J410 IO_L13P_10 H510 IO_L13N_10 J510 IO_L14P_10 L510 IO_L14N_10 M510 IO_L15P_10 N910 IO_L15N_10 N810 IO_L16P_10 K310 IO_L16N_10 L310 IO_L25P_CC_LC_10 T1110 IO_L25N_CC_LC_10 U1110 IO_L26P_10 R410 IO_L26N_10 T410 IO_L27P_10 T1310 IO_L27N_10 U1210 IO_L28P_10 T1010 IO_L28N_VREF_10 T910 IO_L29P_10 R310 IO_L29N_10 T310 IO_L30P_10 T810 IO_L30N_10 U810 IO_L31P_10 T6No Connects inFX100 DevicesVirtex-4 FPGA Packaging and Pinout Specification www.xilinx.com 211UG075 (v3.3) September 19, 2008

Chapter 2: Pinout TablesRTable 2-8: FF1517 Package — FX140 and FX100 Devices (Continued)Bank Pin Description Pin Number10 IO_L31N_10 T510 IO_L32P_10 U1010 IO_L32N_10 V9No Connects inFX100 Devices11 IO_L17P_11 AG3311 IO_L17N_11 AG3211 IO_L18P_11 AH3411 IO_L18N_11 AJ3411 IO_L19P_11 AJ3711 IO_L19N_11 AK3711 IO_L20P_11 AJ3611 IO_L20N_VREF_11 AK3611 IO_L21P_11 AF3011 IO_L21N_11 AG3011 IO_L22P_11 AL3611 IO_L22N_11 AM3611 IO_L23P_VRN_11 AH3311 IO_L23N_VRP_11 AJ3211 IO_L24P_CC_LC_11 AK3411 IO_L24N_CC_LC_11 AL3411 IO_L1P_11 AC3011 IO_L1N_11 AC2911 IO_L2P_11 AC2811 IO_L2N_11 AD2711 IO_L3P_11 AD3511 IO_L3N_11 AD3411 IO_L4P_11 AC3211 IO_L4N_VREF_11 AB3111 IO_L5P_11 AD3111 IO_L5N_11 AD3011 IO_L6P_11 AE3711 IO_L6N_11 AD3711 IO_L7P_11 AD2911 IO_L7N_11 AE2911 IO_L8P_CC_LC_11 AE3611 IO_L8N_CC_LC_11 AD36212 www.xilinx.com Virtex-4 FPGA Packaging and Pinout SpecificationUG075 (v3.3) September 19, 2008

RFF1517 Flip-Chip Fine-Pitch BGA PackageTable 2-8: FF1517 Package — FX140 and FX100 Devices (Continued)Bank Pin Description Pin Number11 IO_L9P_CC_LC_11 AE3211 IO_L9N_CC_LC_11 AD3211 IO_L10P_11 AF3511 IO_L10N_11 AG3511 IO_L11P_11 AF3611 IO_L11N_11 AG3611 IO_L12P_11 AE3411 IO_L12N_VREF_11 AF3411 IO_L13P_11 AG3711 IO_L13N_11 AH3711 IO_L14P_11 AF3111 IO_L14N_11 AG3111 IO_L15P_11 AF3311 IO_L15N_11 AE3311 IO_L16P_11 AH3511 IO_L16N_11 AJ3511 IO_L25P_CC_LC_11 AF2911 IO_L25N_CC_LC_11 AE2811 IO_L26P_11 AN3511 IO_L26N_11 AN3411 IO_L27P_11 AM3711 IO_L27N_11 AN3711 IO_L28P_11 AH3011 IO_L28N_VREF_11 AH2911 IO_L29P_11 AL3511 IO_L29N_11 AM3511 IO_L30P_11 AM3311 IO_L30N_11 AN3311 IO_L31P_11 AK3311 IO_L31N_11 AK3211 IO_L32P_11 AG2811 IO_L32N_11 AF28No Connects inFX100 Devices12 IO_L17P_12 AM612 IO_L17N_12 AL612 IO_L18P_12 AH7Virtex-4 FPGA Packaging and Pinout Specification www.xilinx.com 213UG075 (v3.3) September 19, 2008

Chapter 2: Pinout TablesRTable 2-8: FF1517 Package — FX140 and FX100 Devices (Continued)Bank Pin Description Pin Number12 IO_L18N_12 AG712 IO_L19P_12 AG1012 IO_L19N_12 AF1012 IO_L20P_12 AM512 IO_L20N_VREF_12 AL512 IO_L21P_12 AT412 IO_L21N_12 AR412 IO_L22P_12 AK612 IO_L22N_12 AJ612 IO_L23P_VRN_12 AR612 IO_L23N_VRP_12 AP612 IO_L24P_CC_LC_12 AH812 IO_L24N_CC_LC_12 AG812 IO_L1P_12 AB1212 IO_L1N_12 AB1112 IO_L2P_12 AB1012 IO_L2N_12 AC1012 IO_L3P_12 AA1412 IO_L3N_12 AA1312 IO_L4P_12 AC912 IO_L4N_VREF_12 AC812 IO_L5P_12 AC1212 IO_L5N_12 AD1112 IO_L6P_12 AD1012 IO_L6N_12 AD912 IO_L7P_12 AC1312 IO_L7N_12 AB1312 IO_L8P_CC_LC_12 AD712 IO_L8N_CC_LC_12 AC712 IO_L9P_CC_LC_12 AF912 IO_L9N_CC_LC_12 AF812 IO_L10P_12 AE812 IO_L10N_12 AE712 IO_L11P_12 AC1412 IO_L11N_12 AB1512 IO_L12P_12 AG612 IO_L12N_VREF_12 AG5No Connects inFX100 Devices214 www.xilinx.com Virtex-4 FPGA Packaging and Pinout SpecificationUG075 (v3.3) September 19, 2008

RFF1517 Flip-Chip Fine-Pitch BGA PackageTable 2-8: FF1517 Package — FX140 and FX100 Devices (Continued)Bank Pin Description Pin Number12 IO_L13P_12 AN312 IO_L13N_12 AM312 IO_L14P_12 AJ512 IO_L14N_12 AH512 IO_L15P_12 AP412 IO_L15N_12 AN412 IO_L16P_12 AL412 IO_L16N_12 AL312 IO_L25P_CC_LC_12 AU512 IO_L25N_CC_LC_12 AT512 IO_L26P_12 AK712 IO_L26N_12 AJ712 IO_L27P_12 AH1012 IO_L27N_12 AH912 IO_L28P_12 AT312 IO_L28N_VREF_12 AR312 IO_L29P_12 AM812 IO_L29N_12 AM712 IO_L30P_12 AP512 IO_L30N_12 AN512 IO_L31P_12 AU612 IO_L31N_12 AT612 IO_L32P_12 AL812 IO_L32N_12 AK8No Connects inFX100 Devices13 IO_L17P_13 AA3613 IO_L17N_13 AB3613 IO_L18P_13 AA3513 IO_L18N_13 AB3513 IO_L19P_13 W3013 IO_L19N_13 W2913 IO_L20P_13 AB3713 IO_L20N_VREF_13 AC3713 IO_L21P_13 Y3213 IO_L21N_13 Y3113 IO_L22P_13 AB23Virtex-4 FPGA Packaging and Pinout Specification www.xilinx.com 215UG075 (v3.3) September 19, 2008

Chapter 2: Pinout TablesRTable 2-8: FF1517 Package — FX140 and FX100 Devices (Continued)Bank Pin Description Pin Number13 IO_L22N_13 AA2313 IO_L23P_VRN_13 AA3313 IO_L23N_VRP_13 AB3313 IO_L24P_CC_LC_13 AA2513 IO_L24N_CC_LC_13 AA2413 IO_L1P_13 N3713 IO_L1N_13 M3713 IO_L2P_13 K3713 IO_L2N_13 K3613 IO_L3P_13 R3613 IO_L3N_13 P3613 IO_L4P_13 M3613 IO_L4N_VREF_13 L3613 IO_L5P_13 R3713 IO_L5N_13 P3713 IO_L6P_13 R3413 IO_L6N_13 P3513 IO_L7P_13 U3613 IO_L7N_13 T3613 IO_L8P_CC_LC_13 T3513 IO_L8N_CC_LC_13 T3413 IO_L9P_CC_LC_13 V3713 IO_L9N_CC_LC_13 U3713 IO_L10P_13 V3513 IO_L10N_13 U3513 IO_L11P_13 V3413 IO_L11N_13 V3313 IO_L12P_13 W3713 IO_L12N_VREF_13 Y3713 IO_L13P_13 W3613 IO_L13N_13 Y3613 IO_L14P_13 W3213 IO_L14N_13 Y3313 IO_L15P_13 W3513 IO_L15N_13 W3413 IO_L16P_13 Y3413 IO_L16N_13 AA34No Connects inFX100 Devices216 www.xilinx.com Virtex-4 FPGA Packaging and Pinout SpecificationUG075 (v3.3) September 19, 2008

RFF1517 Flip-Chip Fine-Pitch BGA PackageTable 2-8: FF1517 Package — FX140 and FX100 Devices (Continued)Bank Pin Description Pin Number13 IO_L25P_CC_LC_13 AC3513 IO_L25N_CC_LC_13 AC3413 IO_L26P_13 AA2613 IO_L26N_13 Y2613 IO_L27P_13 AA3113 IO_L27N_13 AA3013 IO_L28P_13 AC2513 IO_L28N_VREF_13 AC2413 IO_L29P_13 AB2813 IO_L29N_13 AB2713 IO_L30P_13 AB2613 IO_L30N_13 AB2513 IO_L31P_13 AA2913 IO_L31N_13 Y2913 IO_L32P_13 AA2813 IO_L32N_13 Y27No Connects inFX100 Devices14 IO_L17P_14 AF414 IO_L17N_14 AE414 IO_L18P_14 AC514 IO_L18N_14 AB514 IO_L19P_14 W1714 IO_L19N_14 W1614 IO_L20P_14 AD414 IO_L20N_VREF_14 AC414 IO_L21P_14 W1414 IO_L21N_14 Y1414 IO_L22P_14 AB714 IO_L22N_14 AA614 IO_L23P_VRN_14 W1214 IO_L23N_VRP_14 W1114 IO_L24P_CC_LC_14 AF314 IO_L24N_CC_LC_14 AE314 IO_L1P_14 U614 IO_L1N_14 U514 IO_L2P_14 V3Virtex-4 FPGA Packaging and Pinout Specification www.xilinx.com 217UG075 (v3.3) September 19, 2008

Chapter 2: Pinout TablesRTable 2-8: FF1517 Package — FX140 and FX100 Devices (Continued)Bank Pin Description Pin Number14 IO_L2N_14 U314 IO_L3P_14 U1514 IO_L3N_14 V1414 IO_L4P_14 W414 IO_L4N_VREF_14 V414 IO_L5P_14 Y614 IO_L5N_14 W614 IO_L6P_14 W514 IO_L6N_14 V514 IO_L7P_14 U1614 IO_L7N_14 V1714 IO_L8P_CC_LC_14 W714 IO_L8N_CC_LC_14 V714 IO_L9P_CC_LC_14 AC314 IO_L9N_CC_LC_14 AB314 IO_L10P_14 Y414 IO_L10N_14 Y314 IO_L11P_14 V1314 IO_L11N_14 V1214 IO_L12P_14 AA514 IO_L12N_VREF_14 AA414 IO_L13P_14 Y1114 IO_L13N_14 W1014 IO_L14P_14 Y914 IO_L14N_14 W914 IO_L15P_14 V1514 IO_L15N_14 W1514 IO_L16P_14 Y814 IO_L16N_14 Y714 IO_L25P_CC_LC_14 AJ414 IO_L25N_CC_LC_14 AH414 IO_L26P_14 AD614 IO_L26N_14 AD514 IO_L27P_14 Y1314 IO_L27N_14 Y1214 IO_L28P_14 AA914 IO_L28N_VREF_14 AA8No Connects inFX100 Devices218 www.xilinx.com Virtex-4 FPGA Packaging and Pinout SpecificationUG075 (v3.3) September 19, 2008

RFF1517 Flip-Chip Fine-Pitch BGA PackageTable 2-8: FF1517 Package — FX140 and FX100 Devices (Continued)Bank Pin Description Pin Number14 IO_L29P_14 AK414 IO_L29N_14 AK314 IO_L30P_14 AH314 IO_L30N_14 AG314 IO_L31P_14 AA1114 IO_L31N_14 AA1014 IO_L32P_14 AE614 IO_L32N_14 AF5No Connects inFX100 Devices0 VCCO_0 (1) AA170 VCCO_0 (1) Y200 VCCO_0 (1) W231 VCCO_1 H161 VCCO_1 L171 VCCO_1 D181 VCCO_1 P181 VCCO_1 N211 VCCO_1 F221 VCCO_1 J231 VCCO_1 M242 VCCO_2 AF222 VCCO_2 AT222 VCCO_2 AJ232 VCCO_2 AM242 VCCO_2 AH162 VCCO_2 AL172 VCCO_2 AP182 VCCO_2 AU182 VCCO_2 AG193 VCCO_3 G193 VCCO_3 K204 VCCO_4 AK204 VCCO_4 AN215 VCCO_5 D225 VCCO_5 E255 VCCO_5 H26Virtex-4 FPGA Packaging and Pinout Specification www.xilinx.com 219UG075 (v3.3) September 19, 2008

Chapter 2: Pinout TablesRTable 2-8: FF1517 Package — FX140 and FX100 Devices (Continued)Bank Pin Description Pin Number5 VCCO_5 L275 VCCO_5 D285 VCCO_5 G295 VCCO_5 K305 VCCO_5 C315 VCCO_5 F326 VCCO_6 C36 VCCO_6 E56 VCCO_6 D86 VCCO_6 G96 VCCO_6 K106 VCCO_6 C116 VCCO_6 F126 VCCO_6 J136 VCCO_6 E157 VCCO_7 AR257 VCCO_7 AL277 VCCO_7 AP287 VCCO_7 AU297 VCCO_7 AK307 VCCO_7 AN317 VCCO_7 AT327 VCCO_7 AR357 VCCO_7 AU378 VCCO_8 AP88 VCCO_8 AU98 VCCO_8 AK108 VCCO_8 AN118 VCCO_8 AT128 VCCO_8 AJ138 VCCO_8 AM148 VCCO_8 AR159 VCCO_9 V269 VCCO_9 U299 VCCO_9 N319 VCCO_9 T329 VCCO_9 J33No Connects inFX100 Devices220 www.xilinx.com Virtex-4 FPGA Packaging and Pinout SpecificationUG075 (v3.3) September 19, 2008

RFF1517 Flip-Chip Fine-Pitch BGA PackageTable 2-8: FF1517 Package — FX140 and FX100 Devices (Continued)Bank Pin Description Pin Number9 VCCO_9 M349 VCCO_9 E359 VCCO_9 H369 VCCO_9 C379 VCCO_9 L3710 VCCO_10 J310 VCCO_10 M410 VCCO_10 R510 VCCO_10 H610 VCCO_10 L710 VCCO_10 P810 VCCO_10 U910 VCCO_10 N1110 VCCO_10 T1211 VCCO_11 AD2811 VCCO_11 AG2911 VCCO_11 AC3111 VCCO_11 AF3211 VCCO_11 AJ3311 VCCO_11 AM3411 VCCO_11 AE3511 VCCO_11 AH3611 VCCO_11 AL3712 VCCO_12 AU312 VCCO_12 AM412 VCCO_12 AR512 VCCO_12 AH612 VCCO_12 AL712 VCCO_12 AD812 VCCO_12 AG912 VCCO_12 AC1112 VCCO_12 AB1413 VCCO_13 AB2413 VCCO_13 AA2713 VCCO_13 Y3013 VCCO_13 W3313 VCCO_13 AB34No Connects inFX100 DevicesVirtex-4 FPGA Packaging and Pinout Specification www.xilinx.com 221UG075 (v3.3) September 19, 2008

Chapter 2: Pinout TablesRTable 2-8: FF1517 Package — FX140 and FX100 Devices (Continued)Bank Pin Description Pin Number13 VCCO_13 R3513 VCCO_13 V3613 VCCO_13 AA3714 VCCO_14 W314 VCCO_14 AJ314 VCCO_14 AB414 VCCO_14 AE514 VCCO_14 V614 VCCO_14 AA714 VCCO_14 Y1014 VCCO_14 W1314 VCCO_14 V16No Connects inFX100 DevicesN/A AVCCAUXRXA_101 B22N/A RXPPADA_101 A21N/A VTRXA_101 A23N/A RXNPADA_101 A22N/A AVCCAUXMGT_101 B29N/A AVCCAUXTX_101 B26N/A VTTXA_101 B24N/A TXPPADA_101 A24N/A TXNPADA_101 A25N/A VTTXB_101 B27N/A TXPPADB_101 A26N/A TXNPADB_101 A27N/A AVCCAUXRXB_101 B30N/A RXPPADB_101 A29N/A VTRXB_101 A28N/A RXNPADB_101 A30N/A AVCCAUXRXA_102 B32N/A RXPPADA_102 A31N/A VTRXA_102 A33N/A RXNPADA_102 A32N/A AVCCAUXMGT_102 C38N/A AVCCAUXTX_102 B36222 www.xilinx.com Virtex-4 FPGA Packaging and Pinout SpecificationUG075 (v3.3) September 19, 2008

RFF1517 Flip-Chip Fine-Pitch BGA PackageTable 2-8: FF1517 Package — FX140 and FX100 Devices (Continued)Bank Pin Description Pin NumberN/A VTTXA_102 B34N/A TXPPADA_102 A34N/A TXNPADA_102 A35N/A VTTXB_102 B37N/A TXPPADB_102 A36N/A TXNPADB_102 A37N/A AVCCAUXRXB_102 D38N/A RXPPADB_102 C39N/A VTRXB_102 B38N/A RXNPADB_102 D39N/A MGTCLK_P_102 F39N/A MGTCLK_N_102 G39No Connects inFX100 DevicesN/A AVCCAUXRXA_103 K38N/A RXPPADA_103 J39N/A VTRXA_103 L39N/A RXNPADA_103 K39N/A AVCCAUXMGT_103 U38N/A AVCCAUXTX_103 P38N/A VTTXA_103 M38N/A TXPPADA_103 M39N/A TXNPADA_103 N39N/A VTTXB_103 R38N/A TXPPADB_103 P39N/A TXNPADB_103 R39N/A AVCCAUXRXB_103 V38N/A RXPPADB_103 U39N/A VTRXB_103 T39N/A RXNPADB_103 V39N/A AVCCAUXRXA_104 AA38 NCN/A RXPPADA_104 Y39 NCN/A VTRXA_104 AB39 NCN/A RXNPADA_104 AA39 NCN/A AVCCAUXMGT_104 AH38 NCN/A AVCCAUXTX_104 AE38 NCVirtex-4 FPGA Packaging and Pinout Specification www.xilinx.com 223UG075 (v3.3) September 19, 2008

Chapter 2: Pinout TablesRTable 2-8: FF1517 Package — FX140 and FX100 Devices (Continued)Bank Pin Description Pin NumberNo Connects inFX100 DevicesN/A VTTXA_104 AC38 NCN/A TXPPADA_104 AC39 NCN/A TXNPADA_104 AD39 NCN/A VTTXB_104 AF38 NCN/A TXPPADB_104 AE39 NCN/A TXNPADB_104 AF39 NCN/A AVCCAUXRXB_104 AJ38 NCN/A RXPPADB_104 AH39 NCN/A VTRXB_104 AG39 NCN/A RXNPADB_104 AJ39 NCN/A AVCCAUXRXA_105 AM38N/A RXPPADA_105 AL39N/A VTRXA_105 AN39N/A RXNPADA_105 AM39N/A AVCCAUXMGT_105 AV37N/A AVCCAUXTX_105 AT38N/A VTTXA_105 AP38N/A TXPPADA_105 AP39N/A TXNPADA_105 AR39N/A VTTXB_105 AU38N/A TXPPADB_105 AT39N/A TXNPADB_105 AU39N/A AVCCAUXRXB_105 AV36N/A RXPPADB_105 AW37N/A VTRXB_105 AV38N/A RXNPADB_105 AW36N/A MGTCLK_P_105 AW34N/A MGTCLK_N_105 AW33N/A RTERM_105 AV34N/A MGTVREF_105 AV32N/A AVCCAUXRXA_106 AV30N/A RXPPADA_106 AW31N/A VTRXA_106 AW29N/A RXNPADA_106 AW30224 www.xilinx.com Virtex-4 FPGA Packaging and Pinout SpecificationUG075 (v3.3) September 19, 2008

RFF1517 Flip-Chip Fine-Pitch BGA PackageTable 2-8: FF1517 Package — FX140 and FX100 Devices (Continued)Bank Pin Description Pin NumberN/A AVCCAUXMGT_106 AV22N/A AVCCAUXTX_106 AV25N/A VTTXA_106 AV28N/A TXPPADA_106 AW28N/A TXNPADA_106 AW27N/A VTTXB_106 AV24N/A TXPPADB_106 AW25N/A TXNPADB_106 AW24N/A AVCCAUXRXB_106 AV21N/A RXPPADB_106 AW22N/A VTRXB_106 AW23N/A RXNPADB_106 AW21No Connects inFX100 DevicesN/A AVCCAUXRXA_109 AV10N/A RXPPADA_109 AW9N/A VTRXA_109 AW11N/A RXNPADA_109 AW10N/A AVCCAUXMGT_109 AV18N/A AVCCAUXTX_109 AV15N/A VTTXA_109 AV12N/A TXPPADA_109 AW12N/A TXNPADA_109 AW13N/A VTTXB_109 AV16N/A TXPPADB_109 AW15N/A TXNPADB_109 AW16N/A AVCCAUXRXB_109 AV19N/A RXPPADB_109 AW18N/A VTRXB_109 AW17N/A RXNPADB_109 AW19N/A AVCCAUXRXA_110 AM2N/A RXPPADA_110 AL1N/A VTRXA_110 AN1N/A RXNPADA_110 AM1N/A AVCCAUXMGT_110 AV3N/A AVCCAUXTX_110 AT2Virtex-4 FPGA Packaging and Pinout Specification www.xilinx.com 225UG075 (v3.3) September 19, 2008

Chapter 2: Pinout TablesRTable 2-8: FF1517 Package — FX140 and FX100 Devices (Continued)Bank Pin Description Pin NumberN/A VTTXA_110 AP2N/A TXPPADA_110 AP1N/A TXNPADA_110 AR1N/A VTTXB_110 AU2N/A TXPPADB_110 AT1N/A TXNPADB_110 AU1N/A AVCCAUXRXB_110 AV4N/A RXPPADB_110 AW3N/A VTRXB_110 AV2N/A RXNPADB_110 AW4N/A MGTCLK_P_110 AW6N/A MGTCLK_N_110 AW7N/A RTERM_110 AV6N/A MGTVREF_110 AV8No Connects inFX100 DevicesN/A AVCCAUXRXA_111 AA2 NCN/A RXPPADA_111 Y1 NCN/A VTRXA_111 AB1 NCN/A RXNPADA_111 AA1 NCN/A AVCCAUXMGT_111 AH2 NCN/A AVCCAUXTX_111 AE2 NCN/A VTTXA_111 AC2 NCN/A TXPPADA_111 AC1 NCN/A TXNPADA_111 AD1 NCN/A VTTXB_111 AF2 NCN/A TXPPADB_111 AE1 NCN/A TXNPADB_111 AF1 NCN/A AVCCAUXRXB_111 AJ2 NCN/A RXPPADB_111 AH1 NCN/A VTRXB_111 AG1 NCN/A RXNPADB_111 AJ1 NCN/A AVCCAUXRXA_112 K2N/A RXPPADA_112 J1N/A VTRXA_112 L1N/A RXNPADA_112 K1226 www.xilinx.com Virtex-4 FPGA Packaging and Pinout SpecificationUG075 (v3.3) September 19, 2008

RFF1517 Flip-Chip Fine-Pitch BGA PackageTable 2-8: FF1517 Package — FX140 and FX100 Devices (Continued)Bank Pin Description Pin NumberN/A AVCCAUXMGT_112 U2N/A AVCCAUXTX_112 P2N/A VTTXA_112 M2N/A TXPPADA_112 M1N/A TXNPADA_112 N1N/A VTTXB_112 R2N/A TXPPADB_112 P1N/A TXNPADB_112 R1N/A AVCCAUXRXB_112 V2N/A RXPPADB_112 U1N/A VTRXB_112 T1N/A RXNPADB_112 V1No Connects inFX100 DevicesN/A AVCCAUXRXA_113 B8N/A RXPPADA_113 A9N/A VTRXA_113 A7N/A RXNPADA_113 A8N/A AVCCAUXMGT_113 C2N/A AVCCAUXTX_113 B4N/A VTTXA_113 B6N/A TXPPADA_113 A6N/A TXNPADA_113 A5N/A VTTXB_113 B3N/A TXPPADB_113 A4N/A TXNPADB_113 A3N/A AVCCAUXRXB_113 D2N/A RXPPADB_113 C1N/A VTRXB_113 B2N/A RXNPADB_113 D1N/A MGTCLK_P_113 F1N/A MGTCLK_N_113 G1N/A AVCCAUXRXA_114 B18N/A RXPPADA_114 A19N/A VTRXA_114 A17N/A RXNPADA_114 A18Virtex-4 FPGA Packaging and Pinout Specification www.xilinx.com 227UG075 (v3.3) September 19, 2008

Chapter 2: Pinout TablesRTable 2-8: FF1517 Package — FX140 and FX100 Devices (Continued)Bank Pin Description Pin NumberN/A AVCCAUXMGT_114 B11N/A AVCCAUXTX_114 B14N/A VTTXA_114 B16N/A TXPPADA_114 A16N/A TXNPADA_114 A15N/A VTTXB_114 B13N/A TXPPADB_114 A14N/A TXNPADB_114 A13N/A AVCCAUXRXB_114 B10N/A RXPPADB_114 A11N/A VTRXB_114 A12N/A RXNPADB_114 A10No Connects inFX100 DevicesN/A GNDA_101 B20N/A GNDA_101 B21N/A GNDA_101 B23N/A GNDA_101 B25N/A GNDA_101 B28N/A GNDA_102 B31N/A GNDA_102 B33N/A GNDA_102 B35N/A GNDA_102 A38N/A GNDA_102 E38N/A GNDA_102 F38N/A GNDA_102 G38N/A GNDA_102 B39N/A GNDA_102 E39N/A GNDA_102 H39N/A GNDA_102 H38N/A GNDA_103 J38N/A GNDA_103 L38N/A GNDA_103 N38N/A GNDA_103 T38N/A GNDA_103 W38N/A GNDA_104 Y38 NCN/A GNDA_104 AB38 NC228 www.xilinx.com Virtex-4 FPGA Packaging and Pinout SpecificationUG075 (v3.3) September 19, 2008

RFF1517 Flip-Chip Fine-Pitch BGA PackageTable 2-8: FF1517 Package — FX140 and FX100 Devices (Continued)Bank Pin Description Pin NumberNo Connects inFX100 DevicesN/A GNDA_104 AD38 NCN/A GNDA_104 AG38 NCN/A GNDA_104 AK38 NCN/A GNDA_104 W39 NCN/A GNDA_105 AV35N/A GNDA_105 AL38N/A GNDA_105 AN38N/A GNDA_105 AR38N/A GNDA_105 AW38N/A GNDA_105 AK39N/A GNDA_105 AV39N/A GNDA_105 AW20N/A GNDA_105 AV23N/A GNDA_105 AV26N/A GNDA_106 AW26N/A GNDA_106 AV27N/A GNDA_106 AV29N/A GNDA_106 AV31N/A GNDA_106 AW32N/A GNDA_106 AV33N/A GNDA_106 AW35N/A GNDA_109 AV9N/A GNDA_109 AV11N/A GNDA_109 AV13N/A GNDA_109 AV14N/A GNDA_109 AW14N/A GNDA_109 AV17N/A GNDA_109 AV20N/A GNDA_110 AK1N/A GNDA_110 AV1N/A GNDA_110 AL2N/A GNDA_110 AN2N/A GNDA_110 AR2N/A GNDA_110 AW2N/A GNDA_110 AV5N/A GNDA_110 AW5N/A GNDA_110 AV7Virtex-4 FPGA Packaging and Pinout Specification www.xilinx.com 229UG075 (v3.3) September 19, 2008

Chapter 2: Pinout TablesRTable 2-8: FF1517 Package — FX140 and FX100 Devices (Continued)Bank Pin Description Pin NumberNo Connects inFX100 DevicesN/A GNDA_110 AW8N/A GNDA_111 W1 NCN/A GNDA_111 Y2 NCN/A GNDA_111 AB2 NCN/A GNDA_111 AD2 NCN/A GNDA_111 AG2 NCN/A GNDA_111 AK2 NCN/A GNDA_112 H2N/A GNDA_112 J2N/A GNDA_112 L2N/A GNDA_112 N2N/A GNDA_112 T2N/A GNDA_113 W2N/A GNDA_113 B1N/A GNDA_113 E1N/A GNDA_113 H1N/A GNDA_113 A2N/A GNDA_113 E2N/A GNDA_113 F2N/A GNDA_113 G2N/A GNDA_113 B5N/A GNDA_113 B7N/A GNDA_113 B9N/A GNDA_114 B12N/A GNDA_114 B15N/A GNDA_114 B17N/A GNDA_114 B19N/A GNDA_114 A20N/A VREFN_SM (2) AT21N/A VREFP_SM (2) AT20N/A AVDD_SM (3) AT19N/A VN_SM (2) AU21N/A VP_SM (2) AU20N/A AVSS_SM (2) AU19230 www.xilinx.com Virtex-4 FPGA Packaging and Pinout SpecificationUG075 (v3.3) September 19, 2008

RFF1517 Flip-Chip Fine-Pitch BGA PackageTable 2-8: FF1517 Package — FX140 and FX100 Devices (Continued)Bank Pin Description Pin NumberN/A VREFN_ADC (2) D21N/A VREFP_ADC (2) D20N/A AVDD_ADC (3) D19N/A VN_ADC (2) C21N/A VP_ADC (2) C20N/A AVSS_ADC (2) C19No Connects inFX100 DevicesN/A GND D3N/A GND P3N/A GND AA3N/A GND AD3N/A GND AP3N/A GND G4N/A GND U4N/A GND AG4N/A GND AU4N/A GND K5N/A GND Y5N/A GND AK5N/A GND C6N/A GND N6N/A GND AC6N/A GND AN6N/A GND F7N/A GND T7N/A GND AF7N/A GND AT7N/A GND J8N/A GND W8N/A GND AJ8N/A GND M9N/A GND AB9N/A GND AM9N/A GND E10N/A GND R10N/A GND AE10Virtex-4 FPGA Packaging and Pinout Specification www.xilinx.com 231UG075 (v3.3) September 19, 2008

Chapter 2: Pinout TablesRTable 2-8: FF1517 Package — FX140 and FX100 Devices (Continued)Bank Pin Description Pin NumberN/A GND AR10N/A GND H11N/A GND V11N/A GND AF11N/A GND AH11N/A GND L12N/A GND AA12N/A GND AE12N/A GND AG12N/A GND AL12N/A GND D13N/A GND M13N/A GND P13N/A GND AD13N/A GND AF13N/A GND AP13N/A GND G14N/A GND L14N/A GND N14N/A GND R14N/A GND U14N/A GND AE14N/A GND AG14N/A GND AU14N/A GND K15N/A GND M15N/A GND P15N/A GND T15N/A GND Y15N/A GND AD15N/A GND AF15N/A GND AK15N/A GND C16N/A GND N16N/A GND R16N/A GND AC16N/A GND AE16No Connects inFX100 Devices232 www.xilinx.com Virtex-4 FPGA Packaging and Pinout SpecificationUG075 (v3.3) September 19, 2008

RFF1517 Flip-Chip Fine-Pitch BGA PackageTable 2-8: FF1517 Package — FX140 and FX100 Devices (Continued)Bank Pin Description Pin NumberN/A GND AN16N/A GND F17N/A GND T17N/A GND AD17N/A GND AF17N/A GND AT17N/A GND J18N/A GND U18N/A GND W18N/A GND AC18N/A GND AE18N/A GND AJ18N/A GND M19N/A GND T19N/A GND V19N/A GND AB19N/A GND AD19N/A GND AF19N/A GND AM19N/A GND E20N/A GND R20N/A GND U20N/A GND AC20N/A GND AE20N/A GND AR20N/A GND H21N/A GND P21N/A GND T21N/A GND V21N/A GND AB21N/A GND AD21N/A GND AH21N/A GND C22N/A GND L22N/A GND R22N/A GND U22N/A GND AA22No Connects inFX100 DevicesVirtex-4 FPGA Packaging and Pinout Specification www.xilinx.com 233UG075 (v3.3) September 19, 2008

Chapter 2: Pinout TablesRTable 2-8: FF1517 Package — FX140 and FX100 Devices (Continued)Bank Pin Description Pin NumberN/A GND AC22N/A GND AL22N/A GND AU22N/A GND D23N/A GND P23N/A GND T23N/A GND AD23N/A GND AP23N/A GND G24N/A GND R24N/A GND U24N/A GND AE24N/A GND AG24N/A GND AU24N/A GND K25N/A GND P25N/A GND T25N/A GND Y25N/A GND AD25N/A GND AF25N/A GND AH25N/A GND AK25N/A GND C26N/A GND N26N/A GND R26N/A GND AC26N/A GND AE26N/A GND AG26N/A GND AJ26N/A GND AN26N/A GND F27N/A GND P27N/A GND T27N/A GND AF27N/A GND AH27N/A GND AT27N/A GND J28No Connects inFX100 Devices234 www.xilinx.com Virtex-4 FPGA Packaging and Pinout SpecificationUG075 (v3.3) September 19, 2008

RFF1517 Flip-Chip Fine-Pitch BGA PackageTable 2-8: FF1517 Package — FX140 and FX100 Devices (Continued)Bank Pin Description Pin NumberN/A GND N28N/A GND R28N/A GND W28N/A GND AJ28N/A GND M29N/A GND P29N/A GND AB29N/A GND AM29N/A GND E30N/A GND R30N/A GND AE30N/A GND AR30N/A GND H31N/A GND V31N/A GND AH31N/A GND L32N/A GND AA32N/A GND AL32N/A GND D33N/A GND P33N/A GND AD33N/A GND AP33N/A GND G34N/A GND U34N/A GND AG34N/A GND AU34N/A GND K35N/A GND Y35N/A GND AK35N/A GND C36N/A GND N36N/A GND AC36N/A GND AN36N/A GND F37N/A GND T37N/A GND AF37N/A GND AT37No Connects inFX100 DevicesVirtex-4 FPGA Packaging and Pinout Specification www.xilinx.com 235UG075 (v3.3) September 19, 2008

Chapter 2: Pinout TablesRTable 2-8: FF1517 Package — FX140 and FX100 Devices (Continued)Bank Pin Description Pin NumberNo Connects inFX100 DevicesN/A VCCAUX J7N/A VCCAUX U7N/A VCCAUX M8N/A VCCAUX AB8N/A VCCAUX R9N/A VCCAUX AE9N/A VCCAUX V10N/A VCCAUX K12N/A VCCAUX AM12N/A VCCAUX J15N/A VCCAUX AL15N/A VCCAUX AK18N/A VCCAUX AA19N/A VCCAUX W21N/A VCCAUX K22N/A VCCAUX J25N/A VCCAUX AL25N/A VCCAUX AK28N/A VCCAUX R29N/A VCCAUX M30N/A VCCAUX AB30N/A VCCAUX AE31N/A VCCAUX V32N/A VCCAUX AH32N/A VCCAUX AC33N/A VCCAUX AL33N/A VCCINT AB6N/A VCCINT AF6N/A VCCINT V8N/A VCCINT L9N/A VCCINT L11N/A VCCINT AE11N/A VCCINT AG11N/A VCCINT M12N/A VCCINT AD12236 www.xilinx.com Virtex-4 FPGA Packaging and Pinout SpecificationUG075 (v3.3) September 19, 2008

RFF1517 Flip-Chip Fine-Pitch BGA PackageTable 2-8: FF1517 Package — FX140 and FX100 Devices (Continued)Bank Pin Description Pin NumberN/A VCCINT AF12N/A VCCINT L13N/A VCCINT N13N/A VCCINT R13N/A VCCINT U13N/A VCCINT AE13N/A VCCINT AG13N/A VCCINT K14N/A VCCINT M14N/A VCCINT P14N/A VCCINT T14N/A VCCINT AD14N/A VCCINT AF14N/A VCCINT L15N/A VCCINT N15N/A VCCINT R15N/A VCCINT AA15N/A VCCINT AC15N/A VCCINT AE15N/A VCCINT AG15N/A VCCINT AJ15N/A VCCINT P16N/A VCCINT T16N/A VCCINT AD16N/A VCCINT AF16N/A VCCINT N17N/A VCCINT R17N/A VCCINT U17N/A VCCINT AC17N/A VCCINT AE17N/A VCCINT T18N/A VCCINT V18N/A VCCINT AB18N/A VCCINT AD18N/A VCCINT AF18N/A VCCINT AH18N/A VCCINT R19No Connects inFX100 DevicesVirtex-4 FPGA Packaging and Pinout Specification www.xilinx.com 237UG075 (v3.3) September 19, 2008

Chapter 2: Pinout TablesRTable 2-8: FF1517 Package — FX140 and FX100 Devices (Continued)Bank Pin Description Pin NumberN/A VCCINT U19N/A VCCINT W19N/A VCCINT AC19N/A VCCINT AE19N/A VCCINT M20N/A VCCINT P20N/A VCCINT T20N/A VCCINT V20N/A VCCINT AB20N/A VCCINT AD20N/A VCCINT AF20N/A VCCINT AH20N/A VCCINT R21N/A VCCINT U21N/A VCCINT AA21N/A VCCINT AC21N/A VCCINT AE21N/A VCCINT M22N/A VCCINT P22N/A VCCINT T22N/A VCCINT V22N/A VCCINT AB22N/A VCCINT AD22N/A VCCINT AK22N/A VCCINT R23N/A VCCINT U23N/A VCCINT AC23N/A VCCINT AE23N/A VCCINT AG23N/A VCCINT P24N/A VCCINT T24N/A VCCINT AD24N/A VCCINT AF24N/A VCCINT L25N/A VCCINT N25N/A VCCINT R25N/A VCCINT U25No Connects inFX100 Devices238 www.xilinx.com Virtex-4 FPGA Packaging and Pinout SpecificationUG075 (v3.3) September 19, 2008

RFF1517 Flip-Chip Fine-Pitch BGA PackageTable 2-8: FF1517 Package — FX140 and FX100 Devices (Continued)Bank Pin Description Pin NumberNo Connects inFX100 DevicesN/A VCCINT W25N/A VCCINT AE25N/A VCCINT AG25N/A VCCINT AJ25N/A VCCINT P26N/A VCCINT T26N/A VCCINT AD26N/A VCCINT AF26N/A VCCINT AH26N/A VCCINT AK26N/A VCCINT N27N/A VCCINT R27N/A VCCINT AC27N/A VCCINT AE27N/A VCCINT AG27N/A VCCINT AJ27N/A VCCINT P28N/A VCCINT T28N/A VCCINT Y28N/A VCCINT AH28N/A VCCINT N29N/A VCCINT AJ29N/A VCCINT W31N/A VCCINT AJ31N/A VCCINT AB32N/A VCCINT P34Notes:1. This voltage is also referred to as V CC_CONFIG in the Virtex-4 Configuration Guide.2. Connect this reserved pin to GND.3. Connect this reserved pin to 2.5V (sharing the same PCB supply distribution as V CCAUX is acceptable).Virtex-4 FPGA Packaging and Pinout Specification www.xilinx.com 239UG075 (v3.3) September 19, 2008

Chapter 2: Pinout TablesR240 www.xilinx.com Virtex-4 FPGA Packaging and Pinout SpecificationUG075 (v3.3) September 19, 2008

RChapter 3Pinout DiagramsSummaryThis chapter provides pinout diagrams for each Virtex-4 FPGA package/devicecombination.Note that multi-function I/O pins are represented in these diagrams by symbols for onlyone of the pin’s available functions, with precedence given to functionality in the followingorder:• VREF, VRP, or VRN• SM1 – SM7• ADC1 – ADC7• D0 – D31• GC• CC• LCFor example, a pin description such as IO_L25N_CC_SM1_LC_7 is represented with anSM1-SM7 symbol, a pin description such as IO_L4N_GC_VREF_LC_4 is represented witha VREF symbol, and a pin description such as IO_L8P_D17_CC_LC_1 is represented witha D0-D31 symbol.• SF363 Package:• “SF363 Package Pinout Diagram (LX15 and FX12),” page 243• “SF363 Package Pinout Diagram (LX25),” page 244• “SF363 Color-Coded SelectIO and Bank Information,” page 245• FF668 Package:• “FF668 Package Pinout Diagram (LX15, SX25, and FX12),” page 246• “FF668 Package Pinout Diagram (LX25, LX40, LX60, and SX35),” page 247• “FF668 Color-Coded SelectIO and Bank Information,” page 248• FF672 Package:• “FF672 Package Pinout Diagram (FX20),” page 249• “FF672 Package Pinout Diagram (FX40),” page 250• “FF672 Package Pinout Diagram (FX60),” page 251Virtex-4 FPGA Packaging and Pinout Specification www.xilinx.com 241UG075 (v3.3) September 19, 2008

Chapter 3: Pinout DiagramsR• “FF672 Color-Coded SelectIO and Bank Information,” page 252• FF676 Package:• “FF676 Package Pinout Diagram (LX15),” page 253• “FF676 Package Pinout Diagram (LX25),” page 254• “FF676 Color-Coded SelectIO and Bank Information,” page 255• FF1148 Package:• “FF1148 Package Pinout Diagram (LX40, LX60, and SX55),” page 256• “FF1148 Package Pinout Diagram (LX80, LX100, and LX160),” page 257• “FF1148 Color-Coded SelectIO and Bank Information,” page 258• FF1152 Package:• “FF1152 Package Pinout Diagram (FX40),” page 259• “FF1152 Package Pinout Diagram (FX60),” page 260• “FF1152 Package Pinout Diagram (FX100),” page 261• “FF1152 Color-Coded SelectIO and Bank Information,” page 262• FF1513 Package:• “FF1513 Package Pinout Diagram (LX100, LX160, and LX200),” page 263• “FF1513 Color-Coded SelectIO and Bank Information,” page 264• FF1517 Package:• “FF1517 Package Pinout Diagram (FX100),” page 265• “FF1517 Package Pinout Diagram (FX140),” page 266• “FF1517 Color-Coded SelectIO and Bank Information,” page 267242 www.xilinx.com Virtex-4 FPGA Packaging and Pinout SpecificationUG075 (v3.3) September 19, 2008

RSF363 Package Pinout Diagram (LX15 and FX12)SF363 Package Pinout Diagram (LX15 and FX12)ABCDEFGHJKLMNPRTUVWYSF363 (XC4VLX15 and XC4VFX12) - Top View1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20ABCDB N L C Y HEU J D PFGHJKLMNPI O 2 0RM K W A 1TUVn n nWn n nY1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20User I/O PinsDedicated PinsOther PinsIO_LXXY_#Multi-Function Pins:ADC1 - ADC7D0 - D31CCN_GCP_GCLCSM1 - SM7VREFVRNZ ADC P PROG_BC CCLKW PWRDWN_BB CS_BU RDWR_BN D_INS SMD DONEK TCKAHYDOUT_BUSY I TDIHSWAPEN O TDOINITM TMS2 1 0 M2, M1, M0 J TDPL TDNRnGNDRSVDVBATTVCCAUXVCCINTVCCONO CONNECTVRPNotes: 1. SM and ADC functionality in multi-function user I/O pins is reserved for future use.2. Dedicated SM and ADC pins are reserved for future use.UG075_02b_050108Figure 3-1: SF363 Flip-Chip Fine-Pitch BGA Pinout Diagram (LX15 and FX12)Virtex-4 FPGA Packaging and Pinout Specification www.xilinx.com 243UG075 (v3.3) September 19, 2008

Chapter 3: Pinout DiagramsRSF363 Package Pinout Diagram (LX25)ABCDEFGHJKLMNPRTUVWYSF363 (XC4VLX25) - Top View1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20ABCDB N L C Y HEU J D PFGHJKLMNPI O 2 0RM K W A 1TUVS S SWS S SY1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20User I/O PinsDedicated PinsOther PinsIO_LXXY_#Multi-Function Pins:ADC1 - ADC7D0 - D31CCN_GCP_GCLCSM1 - SM7VREFVRNZ ADC P PROG_BC CCLKW PWRDWN_BB CS_BU RDWR_BN D_INS SMD DONEK TCKAHYDOUT_BUSY I TDIHSWAPEN O TDOINITM TMS2 1 0 M2, M1, M0 J TDPL TDNRnGNDRSVDVBATTVCCAUXVCCINTVCCONO CONNECTVRPNotes: 1. SM and ADC functionality in multi-function user I/O pins is reserved for future use.2. Dedicated SM and ADC pins are reserved for future use.UG075_02_050108Figure 3-2: SF363 Flip-Chip Fine-Pitch BGA Pinout Diagram (LX25)244 www.xilinx.com Virtex-4 FPGA Packaging and Pinout SpecificationUG075 (v3.3) September 19, 2008

RSF363 Color-Coded SelectIO and Bank InformationSF363 Color-Coded SelectIO and Bank InformationABCDEFGHJKLMNPRTUVWYSF363 - Top View1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20$ $ $ ! ! ! ! ! ! # # #$ $ $ $ $ ! ! ! ! ! ! ! ! # # # # #$ $ $ $ $ $ ! ! # # # # # #$ $ $ $ # # # #$ $ $ $ # # # #$ $ $ $ $ # # # # #$ $ $ $ # # # #$ $ $ $ $ # # # # #$ $ $ $ $ # # # # #$ $ $ $ $ # # # # #$ $ $ $ # # # #$ $ $ $ $ $ # # # # # #$ $ $ $ # # # #$ $ $ $ # # # #& & & & & & % % % % % %& & & & & % % % % %& & & & & % % % % %& & & & % % % %& & & " " " " " " " " " % % %& " " " " " " " %1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20ABCDEFGHJKLMNPRTUVWYug075_02-color_122104Figure 3-3: SF363 Color-Coded SelectIO and Bank InformationVirtex-4 FPGA Packaging and Pinout Specification www.xilinx.com 245UG075 (v3.3) September 19, 2008

Chapter 3: Pinout DiagramsRFF668 Package Pinout Diagram (LX15, SX25, and FX12)FF668 (XC4VLX15, XC4VSX25, and XC4VFX12) - Top View1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26AABBCCDDEEFFGB N L C Y HGHU J D PHJ n n n n n nn n n n n n JK n n n n n n n nn n n n n n n n KL n n n n n n n nn n n n n n n n LM n n n n n n n nn n n n n n n n n MN n n n n n n nn n n n n n n NP n n n n n n nn n n n n n n PR n n n n n n n n nn n n n n n n n RT n n n n n n n nn n n n n n n n TU n n n n n n n nn n n n n n n n UV n n nn n n VWK W 2 0WYM I O A 1YAAAAABABACACADADAEn n nAEAFn n nAF1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26User I/O PinsDedicated PinsOther PinsIO_LXXY_#Multi-Function Pins:ADC1 - ADC7D0 - D31CCN_GCP_GCLCSM1 - SM7VREFVRNZ ADC P PROG_BC CCLKW PWRDWN_BB CS_BU RDWR_BN D_INS SMD DONEK TCKAHYDOUT_BUSY I TDIHSWAPEN O TDOINITM TMS2 1 0 M2, M1, M0 J TDPL TDNRnGNDRSVDVBATTVCCAUXVCCINTVCCONO CONNECTVRPNotes: 1. SM and ADC functionality in multi-function user I/O pins is reserved for future use.2. Dedicated SM and ADC pins are reserved for future use.UG075_01b_050108Figure 3-4: FF668 Flip-Chip Fine-Pitch BGA Pinout Diagram (LX15, SX25, and FX12)246 www.xilinx.com Virtex-4 FPGA Packaging and Pinout SpecificationUG075 (v3.3) September 19, 2008

RFF668 Package Pinout Diagram (LX25, LX40, LX60, and SX35)FF668 Package Pinout Diagram (LX25, LX40, LX60, and SX35)FF668 (LX25, LX40, LX60, and SX35) - Top ViewABCDEFGHJKLMNPRTUVWYAAABACADAEAF1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26ABCDEFB N L C Y HGU J D PHJKLMNPRTUVK W 2 0WM I O A 1YAAABACADSSSAESSSAF1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26User I/O PinsDedicated PinsOther PinsIO_LXXY_#Multi-Function Pins:ADC1 - ADC7D0 - D31CCN_GCP_GCLCSM1 - SM7VREFVRNZ ADC P PROG_BC CCLKW PWRDWN_BB CS_BU RDWR_BN D_INS SMD DONEK TCKAHYDOUT_BUSY I TDIHSWAPEN O TDOINITM TMS2 1 0 M2, M1, M0 J TDPL TDNRnGNDRSVDVBATTVCCAUXVCCINTVCCONO CONNECTVRPNotes: 1. SM and ADC functionality in multi-function user I/O pins is reserved for future use.2. Dedicated SM and ADC pins are reserved for future use.UG075_01_050108Figure 3-5: FF668 Flip-Chip Fine-Pitch BGA Pinout Diagram (LX25, LX40, LX60, and SX35)Virtex-4 FPGA Packaging and Pinout Specification www.xilinx.com 247UG075 (v3.3) September 19, 2008

Chapter 3: Pinout DiagramsRFF668 Color-Coded SelectIO and Bank InformationABCDEFGHJKLMNPRTUVWYAAABACADAEAFFF668 - Top View1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26$ $ $ $ $ $ $ ! ! ! ! ! ! # # # # # # #$ $ $ $ $ ! ! ! ! ! ! # # # # #$ $ $ $ $ $ $ $ ! ! ! ! # # # # # # # # #$ $ $ $ $ $ $ $ $ $ # # # # # # # # # #$ $ $ $ $ $ $ $ $ # # # # # # # # #$ $ $ $ $ $ $ # # # # # # #$ $ $ $ $ $ $ $ $ $ # # # # # # # # # #$ $ $ $ $ $ $ $ # # # # # # # ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' & & & % % % ' ' '& & & & & & & % % % % % % % %& & & & & & & & & & % % % % % % % % % %& & & & & & & % % % % % % %& & & & & & & & " " % % % % % % % %& & & & & & & & & " " % % % % % % % % %& & & & & & & & " " " " " % % % % % % %& & & & & " " " " % % % % %& & & & & & & " " " % % % % % % %1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26ug075_01-color2_121504Figure 3-6: FF668 Color-Coded SelectIO and Bank InformationABCDEFGHJKLMNPRTUVWYAAABACADAEAF248 www.xilinx.com Virtex-4 FPGA Packaging and Pinout SpecificationUG075 (v3.3) September 19, 2008

EEEEEEEEEERFF672 Package Pinout Diagram (FX20)FF672 Package Pinout Diagram (FX20)FF672 (XC4VFX20) - Top ViewABCDEFGHJKLMNPRTUVWYAAABACADAEAF1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26AVV1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26EEBCDLEJX FX GHn n JXXND H PYnnnnKLn n n B C 2 n n n n n Mn n n n n n n nn n n n n n n n Nn n n n n n n n 0 n n n n n n n n Pn n n n n U O 1 n n nn n Rn nM An n Tn nK I Wn n Un nn n Vn nWn nE Yn nV AAn nABACEADVT G n n n G TAEX Xn n n X XAFVVVVVVEEEVVEVVVVUser I/O PinsDedicated PinsOther PinsIO_LXXY_#Multi-Function Pins:ADC1 - ADC7D0 - D31CCN_GCP_GCLCSM1 - SM7VREFVRNVRPZ ADCS SM GNDC CCLKK TCK GNDAB CS_BI TDI R RSVDN D_INO TDO VBATTD DONEM TMS VCCAUXA DOUT_BUSY J TDP VCCINTH HSWAPEN L TDN VCCOY INITn NO CONNECT2 1 0 M2, M1, M0X MGTCLKP PROG_BG MGTVREFW PWRDWN_BT RTERMU RDWR_BEVVVVEAVCCAUXRXAAVCCAUXRXBAVCCAUXTXAVCCAUXMGTVTRXAVTTXAVTRXBVTTXBRXNPADARXPPADATXPPADATXNPADARXNPADBRXPPADBTXPPADBTXNPADBNotes: 1. SM and ADC functionality in multi-function user I/O pins is reserved for future use.2. Dedicated SM and ADC pins are reserved for future use.UG075_04c_050108Figure 3-7: FF672 Flip-Chip Fine-Pitch BGA Pinout Diagram (FX20)Virtex-4 FPGA Packaging and Pinout Specification www.xilinx.com 249UG075 (v3.3) September 19, 2008

EEEEEE EEEEEEEEChapter 3: Pinout DiagramsRFF672 Package Pinout Diagram (FX40)FF672 (XC4VFX40) - Top ViewABCDEFGHJKLMNPRTUVWYAAABACADAEAF1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26AVV1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26EEBCDLEJX FX GHJXD H PE KXN YV LB C 2MNE0PVU O 1RM ATK I WUVWE YV AAABACEADVTX XG SSSGSSSTX XAEAFVVVVVVVVVEEEEEVVEVV VVVVVUser I/O PinsDedicated PinsOther PinsIO_LXXY_#Multi-Function Pins:ADC1 - ADC7D0 - D31CCN_GCP_GCLCSM1 - SM7VREFVRNVRPZ ADCS SM GNDC CCLKK TCK GNDAB CS_BI TDI R RSVDN D_INO TDO VBATTD DONEM TMS VCCAUXA DOUT_BUSY J TDP VCCINTH HSWAPEN L TDN VCCOY INITn NO CONNECT2 1 0 M2, M1, M0X MGTCLKP PROG_BG MGTVREFW PWRDWN_BT RTERMU RDWR_BEVVVVEAVCCAUXRXAAVCCAUXRXBAVCCAUXTXAVCCAUXMGTVTRXAVTTXAVTRXBVTTXBRXNPADARXPPADATXPPADATXNPADARXNPADBRXPPADBTXPPADBTXNPADBNotes: 1. SM and ADC functionality in multi-function user I/O pins is reserved for future use.2. Dedicated SM and ADC pins are reserved for future use.Figure 3-8: FF672 Flip-Chip Fine-Pitch BGA Pinout Diagram (FX40)UG075_04b_050108250 www.xilinx.com Virtex-4 FPGA Packaging and Pinout SpecificationUG075 (v3.3) September 19, 2008

EEEEEE EEEEEEEERFF672 Package Pinout Diagram (FX60)FF672 Package Pinout Diagram (FX60)FF672 (XC4VFX60) - Top ViewABCDEFGHJKLMNPRTUVWYAAABACADAEAF1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26AVV1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26EEBCDLEJX FX GHJXD H PE KXN YV LB C 2MNE0PVU O 1RM ATK I WUVWE YV AAABACEADVTX XG SSSGSSSTX XAEAFVVVVVVVVVEEEEEVVEVV VVVVVUser I/O PinsDedicated PinsOther PinsIO_LXXY_#Multi-Function Pins:ADC1 - ADC7D0 - D31CCN_GCP_GCLCSM1 - SM7VREFVRNVRPZCADCCCLKSKSMTCKGNDGNDAB CS_BI TDI R RSVDN D_INO TDO VBATTD DONEM TMS VCCAUXA DOUT_BUSY J TDP VCCINTHYHSWAPENINITL TDNnVCCONO CONNECT2 1 0 M2, M1, M0X MGTCLKP PROG_BG MGTVREFW PWRDWN_BT RTERMU RDWR_BEVVVVEAVCCAUXRXAAVCCAUXRXBAVCCAUXTXAVCCAUXMGTVTRXAVTTXAVTRXBVTTXBRXNPADARXPPADATXPPADATXNPADARXNPADBRXPPADBTXPPADBTXNPADBNotes: 1. SM and ADC functionality in multi-function user I/O pins is reserved for future use.2. Dedicated SM and ADC pins are reserved for future use.UG075_04_050108Figure 3-9: FF672 Flip-Chip Fine-Pitch BGA Pinout Diagram (FX60)Virtex-4 FPGA Packaging and Pinout Specification www.xilinx.com 251UG075 (v3.3) September 19, 2008

Chapter 3: Pinout DiagramsRFF672 Color-Coded SelectIO and Bank InformationFF672 - Top View1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26ABCDEFGHJKLMNPRTUVWYAAABACADAEAF$ $ $ $ ! ! ! # #$ $ $ $ $ ! ! # # #$ $ $ $ $ $ $ ! ! ! # # # # # # # #$ $ $ $ $ $ $ $ ! ! ! # # # # # # #$ $ $ $ $ $ $ ! ! # # # # # # #$ $ $ $ $ ! ! ! # # # # # # #$ $ $ $ $ $ $ # # # # # #$ $ $ $ $ $ # # # # # #$ $ $ $ # # # #$ $ $ $ $ # # # # #& & $ $ $ $ # # # #& $ $ ' ' ' # #& & ' ' ' ' ' # # #& & & ' ' ' ' ' %& & ' ' ' % % %& & & & % % % % % %& & & & & % % % % %& & & & % % % % %& & & & & & % % % % % %& & & & & & % % % % % % %& & & & & & & " " " % % % % % % % %& & & & & & & " " % % % % % % % %& & & & & & & " " " % % % % % % % %& & & & & & & & " " " % % % % % % %" "" " "1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26ABCDEFGHJKLMNPRTUVWYAAABACADAEAFug075_04-color-2_121504Figure 3-10: FF672 Color-Coded SelectIO and Bank Information252 www.xilinx.com Virtex-4 FPGA Packaging and Pinout SpecificationUG075 (v3.3) September 19, 2008

RFF676 Package Pinout Diagram (LX15)FF676 Package Pinout Diagram (LX15)ABCDEFGHJKLMNPRTUVWYAAABACADAEAFFF676 (LX15) - Top View1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26ABCnDn nJEn nLFn nn n n Gn n nn n n n n Hn n nn n n n n n Jn n n n nY H P n n n n n Kn n n n n nN Dn n n n Ln n n n n n n B C 2 n n n n n n n Mn n n n n nn n n n n n Nn n n n n n0n n n n n n Pn n n n n n n U O 1n n n n n n n Rn n n nM An n n n n n Tn n n n n K I Wn n n n n Un n n n n nn n n Vn n n n nn n n Wn n nn n Yn n AAn n ABn ACADn n nAEn n nAF1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26User I/O PinsDedicated PinsOther PinsIO_LXXY_#Multi-Function Pins:ADC1 - ADC7D0 - D31CCN_GCP_GCLCSM1 - SM7VREFVRNZ ADC P PROG_BC CCLKW PWRDWN_BB CS_BU RDWR_BN D_INS SMD DONEK TCKAHYDOUT_BUSY I TDIHSWAPEN O TDOINITM TMS2 1 0 M2, M1, M0 J TDPL TDNRnGNDRSVDVBATTVCCAUXVCCINTVCCONO CONNECTVRPNotes: 1. SM and ADC functionality in multi-function user I/O pins is reserved for future use.2. Dedicated SM and ADC pins are reserved for future use.UG075_10a_050108Figure 3-11: FF676 Flip-Chip Fine-Pitch BGA Pinout Diagram (LX15)Virtex-4 FPGA Packaging and Pinout Specification www.xilinx.com 253UG075 (v3.3) September 19, 2008

Chapter 3: Pinout DiagramsRFF676 Package Pinout Diagram (LX25)FF676 (LX25) - Top ViewABCDEFGHJKLMNPRTUVWYAAABACADAEAF1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26ABCDJELFGHJY H PKN DLB C 2MN0PU O 1RM ATK I WUVWYAAABACADSSSAESSSAF1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26User I/O PinsDedicated PinsOther PinsIO_LXXY_#Multi-Function Pins:ADC1 - ADC7D0 - D31CCN_GCP_GCLCSM1 - SM7VREFVRNZ ADC P PROG_BC CCLKW PWRDWN_BB CS_BU RDWR_BN D_INS SMD DONEK TCKAHYDOUT_BUSY I TDIHSWAPEN O TDOINITM TMS2 1 0 M2, M1, M0 J TDPL TDNRnGNDRSVDVBATTVCCAUXVCCINTVCCONO CONNECTVRPNotes: 1. SM and ADC functionality in multi-function user I/O pins is reserved for future use.2. Dedicated SM and ADC pins are reserved for future use.UG075_10_050108Figure 3-12: FF676 Flip-Chip Fine-Pitch BGA Pinout Diagram (LX25)254 www.xilinx.com Virtex-4 FPGA Packaging and Pinout SpecificationUG075 (v3.3) September 19, 2008

RFF676 Color-Coded SelectIO and Bank InformationFF676 Color-Coded SelectIO and Bank InformationFF676 - Top ViewABCDEFGHJKLMNPRTUVWYAAABACADAEAF1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26$ $ $ $ $ $ $ $ ! ! ! # # # # # # # # #$ $ $ $ $ $ $ $ $ ! ! # # # # # # # # # #$ $ $ $ $ $ $ $ $ ! ! ! # # # # # # # # # $ $ $ $ $ $ $ $ ! ! ! # # # # # # # # # $ $ $ $ $ $ $ ! ! # # # # # # # # $ $ $ $ $ $ ! ! ! # # # # # # # $ $ $ $ $ $ # # # # # ' ' ' $ $ $ $ # # ' ' ' ' $ $ $ $ # # ' ' ' ' ' $ $ # # ' ' ' ' ' $ # ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' & % % ' ' ' ' ' & & % % ' ' ' ' ' & & % % % % % ' ' & & % % % % ' ' ' & & & & & % % % % % % % ' '& & & & & & & " " " % % % % % % % % '& & & & & & & & " " % % % % % % % % ' '& & & & & & & & & " " " % % % % % % % % '& & & & & & & & & " " " % % % % % % % % %& & & & & & & & & & " " % % % % % %& & & & & & & & & " " " % % % % %1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 ABCDEFGHJKLMNPRTUVWYAAABACADAEAFug075_10-color2_121504Figure 3-13: FF676 Color-Coded SelectIO and Bank InformationVirtex-4 FPGA Packaging and Pinout Specification www.xilinx.com 255UG075 (v3.3) September 19, 2008

Chapter 3: Pinout DiagramsRFF1148 Package Pinout Diagram (LX40, LX60, and SX55)FF1148 (XC4VLX40, XC4VLX60, and XC4VSX55) - Top View1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34ABCDEFGHJKLMNPRTUVWYAAABACADAEAFAGAHAJAKALAMANAPn n nn n n nn n n nn n n nn n n n nn n n n nn n n nn n n n nn n n n nn n nn n nn n nn n nn n nn n n nn n n nnJLn n nn n nCN Hn n nn n n U D B Y P n n nn n n M K O 2 n n nn n nI 1 0 WASSS SS Sn n nn n nn n nn nn nn nn n nn n n n n nn n n n n nn n n n nn n n n nn n n n n nn n n n nn n n n nn n n nn n n1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34ABCDEFGHJKLMNPRTUVWYAAABACADAEAFAGAHAJAKALAMANAPUser I/O PinsDedicated PinsOther PinsIO_LXXY_#Multi-Function Pins:ADC1 - ADC7D0 - D31CCN_GCP_GCLCSM1 - SM7VREFVRNZ ADC P PROG_BC CCLKW PWRDWN_BB CS_BU RDWR_BN D_INS SMD DONEK TCKAHYDOUT_BUSY I TDIHSWAPEN O TDOINITM TMS2 1 0 M2, M1, M0 J TDPL TDNRnGNDRSVDVBATTVCCAUXVCCINTVCCONO CONNECTVRPNotes: 1. SM and ADC functionality in multi-function user I/O pins is reserved for future use.2. Dedicated SM and ADC pins are reserved for future use.UG075_05b_081408Figure 3-14: FF1148 Flip-Chip Fine-Pitch BGA Pinout Diagram (LX40, LX60, and SX55)256 www.xilinx.com Virtex-4 FPGA Packaging and Pinout SpecificationUG075 (v3.3) September 19, 2008

RFF1148 Package Pinout Diagram (LX80, LX100, and LX160)FF1148 Package Pinout Diagram (LX80, LX100, and LX160)FF1148 (XC4VLX80, XC4VLX100, and XC4VLX160) - Top View1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34ABCDEFGHJKLMNPRTUVWYAAABACADAEAFAGAHAJAKALAMANAPJLZ Z ZZ Z ZCN HU D B Y PM K O 2I 1 0 WASSS SS S1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34ABCDEFGHJKLMNPRTUVWYAAABACADAEAFAGAHAJAKALAMANAPUser I/O PinsDedicated PinsOther PinsIO_LXXY_#ZADCP PROG_BGNDMulti-Function Pins:C CCLKW PWRDWN_BR RSVDADC1 - ADC7D0 - D31CCN_GCP_GCLCSM1 - SM7VREFVRNB CS_BN D_IND DONEA DOUT_BUSYHYHSWAPENINIT2 1 0 M2, M1, M0U RDWR_BS SMK TCKI TDIO TDOM TMSJ TDPL TDNnVBATTVCCAUXVCCINTVCCONO CONNECTVRPNotes: 1. SM and ADC functionality in multi-function user I/O pins is reserved for future use.2. Dedicated SM and ADC pins are reserved for future use.UG075_05_043008Figure 3-15: FF1148 Flip-Chip Fine-Pitch BGA Pinout Diagram (LX80, LX100, and LX160)Virtex-4 FPGA Packaging and Pinout Specification www.xilinx.com 257UG075 (v3.3) September 19, 2008

Chapter 3: Pinout DiagramsRFF1148 Color-Coded SelectIO and Bank InformationFF1148 - Top ViewABCDEFGHJKLMNPRTUVWYAAABACADAEAFAGAHAJAKALAMANAP1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34$ $ $ $ $ $ $ $ $ $ # # # # # # # # # A$ $ $ $ $ $ $ $ $ $ # # # # # # # # # # # B $ $ $ $ $ $ $ $ # # # # # # # # ' ' ' C $ $ $ $ $ $ $ $ # # # # # # # # ' ' D $ $ $ $ $ $ $ $ ! ! ! # # # # # # # # ' ' ' E $ $ $ $ ! ! # # # # # # # # ' ' F $ $ $ $ $ $ ! ! ! # # # # ' ' ' ' G $ $ $ $ $ ! ! ! # # ' ' ' ' ' ' ' H $ $ $ ! ! # # ' ' ' ' ' ' J $ $ ! ! ! # # ' ' ' ' ' ' ' K # # ' ' ' ' ' ' L ' ' ' ' ' ' ' ' M" " " ' ' ' ' ' ' ! ! ! N" " " ' ' ' ' ' ! ! ! ! ! P" " " " " " " ' ' ' ' ' ! ! ! ! ! ! ! ! R" " " " " " ! ! ! ! ! ! ! ! ! ! T" " " " " " " " " " ! ! ! ! ! ! ! ! ! U" " " " " " " " " ! ! ! ! ! ! ! ! ! ! V" " " " " " " " " " ! ! ! ! ! ! W" " " " " " " " ! ! ! ! ! ! ! Y" " " " " ! ! ! AA" " " ! ! ! AB AC & & AD & & " " " % % AE & & " " % % % AF & & " " " % % % % % AG & & & & " " " % % % % % % AH & & & & & & & & " " % % % % AJ & & & & & & & & " " " % % % % % % % % AK & & & & & & & & % % % % % % % % AL & & & & & & & & % % % % % % % % AM& & & & & & & & & & & % % % % % % % % % % AN& & & & & & & & & % % % % % % % % % % AP1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34ug075_05-color2_122104Figure 3-16: FF1148 Color-Coded SelectIO and Bank Information258 www.xilinx.com Virtex-4 FPGA Packaging and Pinout SpecificationUG075 (v3.3) September 19, 2008

EEE E EEEE E EEEERFF1152 Package Pinout Diagram (FX40)FF1152 Package Pinout Diagram (FX40)FF1152 (XC4VFX40) - Top ViewABCDEFGHJKLMNPRTUVWYAAABACADAEAFAGAHAJAKALAMANAP1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34V V VXXVEVEn n n n n n n n n n n n n n n n n n n n nn n n n n n n n n n n n n n n n n n n n n n nJ n n nL n n nXEXVY H PN DB C 2En n n Vn n0n n n n n nn n n n n nU O 1n n n n n n n n nn n n n n n n M An n n n n n n nn n n n n n K I Wn n n n n n n nn n n n n nn n n n n n n nn n n n n n nn n n n n n nE n n n n nn n n n n n nV n n n nn n n nn n n n n nn n nn n n n n nn n n En n nn n n Vn n nn n nn n n nn n n nS S Sn n nS S ST G n n n n n n n n n n n n n n n n n n n n n G TX X n n n n n n n n n n n n n n n n n n n n n X XVVVVEEEV1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34EEVV V VVVVEEVVVABCDEFGHJKLMNPRTUVWYAAABACADAEAFAGAHAJAKALAMANAPUser I/O PinsDedicated PinsOther PinsIO_LXXY_#Multi-Function Pins:ADC1 - ADC7D0 - D31CCN_GCP_GCLCSM1 - SM7VREFVRNVRP21ZCBNDAHY0PWUADCCCLKCS_BD_INDONEDOUT_BUSYHSWAPENINITM2, M1, M0PROG_BPWRDWN_BRDWR_BSKIOMJLSMTCKTDITDOTMSTDPTDNGNDGNDAR RSVDVBATTVCCAUXVCCINTVCCOn NO CONNECTX MGTCLKG MGTVREFT RTERMEVVVVEAVCCAUXRXAAVCCAUXRXBAVCCAUXTXAVCCAUXMGTVTRXAVTTXAVTRXBVTTXBRXNPADARXPPADATXPPADATXNPADARXNPADBRXPPADBTXPPADBTXNPADBNotes: 1. SM and ADC functionality in multi-function user I/O pins is reserved for future use.2. Dedicated SM and ADC pins are reserved for future use.UG075_06_043008Figure 3-17: FF1152 Flip-Chip Fine-Pitch BGA Pinout Diagram (FX40)Virtex-4 FPGA Packaging and Pinout Specification www.xilinx.com 259UG075 (v3.3) September 19, 2008

EEEEE E EEEE E EEEEEEChapter 3: Pinout DiagramsRFF1152 Package Pinout Diagram (FX60)FF1152 (XC4VFX60) - Top ViewABCDEFGHJKLMNPRTUVWYAAABACADAEAFAGAHAJAKALAMANAP1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34V V VXXVEVVVEVVVEEEEVVET GX XEVn n n n n n n nn n n n n n n n nVVVY H PN DB C 20U O 1M AK I WS S SS S SEn n n n nn n n n nJ Z Z ZL Z Z ZEnnnnnnnnEVn n n nn n n n nG TX XEVEV1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34VVVEEVV V VVVVEEVVXXVABCDEFGHJKLMNPRTUVWYAAABACADAEAFAGAHAJAKALAMANAPUser I/O PinsDedicated PinsOther PinsIO_LXXY_#Multi-Function Pins:ADC1 - ADC7D0 - D31CCN_GCP_GCLCSM1 - SM7VREFVRNVRP21ZCBNDAHY0PWUADCCCLKCS_BD_INDONEDOUT_BUSYHSWAPENINITM2, M1, M0PROG_BPWRDWN_BRDWR_BSKIOMJLSMTCKTDITDOTMSTDPTDNRnXGTGNDGNDARSVDVBATTVCCAUXVCCINTVCCONO CONNECTMGTCLKMGTVREFRTERMEVVVVEAVCCAUXRXAAVCCAUXRXBAVCCAUXTXAVCCAUXMGTVTRXAVTTXAVTRXBVTTXBRXNPADARXPPADATXPPADATXNPADARXNPADBRXPPADBTXPPADBTXNPADBNotes: 1. SM and ADC functionality in multi-function user I/O pins is reserved for future use.2. Dedicated SM and ADC pins are reserved for future use.Figure 3-18: FF1152 Flip-Chip Fine-Pitch BGA Pinout Diagram (FX60)UG075_06_050108260 www.xilinx.com Virtex-4 FPGA Packaging and Pinout SpecificationUG075 (v3.3) September 19, 2008

EEEEEEEEE E EEE E EEEEEERFF1152 Package Pinout Diagram (FX100)FF1152 Package Pinout Diagram (FX100)FF1152 (XC4VFX100) - Top ViewUser I/O PinsIO_LXXY_#Multi-Function Pins:ADC1 - ADC7D0 - D31CCN_GCP_GCLCSM1 - SM7VREFVRNVRPABCDEFGHJKLMNPRTUVWYAAABACADAEAFAGAHAJAKALAMANAP1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34VXXEVV VVVVEVVVEEEEZCBNDAHYDONE2 1 0 M2, M1, M0P PROG_BW PWRDWN_BUVEDedicated PinsADCCCLKCS_BD_INDOUT_BUSYHSWAPENINITEVRDWR_BSKIOMJLY H PN DB C 20U O 1M AK I WSMTCKTDITDOTMSTDPTDNVVE EJ Z Z ZL Z Z ZEEEV V VT GX XVVVVVS S SS S SE1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34RnXGTEVVGNDGNDARSVDVBATTVCCAUXVCCINTVCCOVEVNO CONNECTMGTCLKMGTVREFRTERMV VEVVVVG TX XEOther PinsEEEEVEEVAVCCAUXRXAAVCCAUXRXBAVCCAUXTXVTRXAVTTXAVTRXBVTTXBVV V VVVVAVCCAUXMGTVVXXVABCDEFGHJKLMNPRTUVWYAAABACADAEAFAGAHAJAKALAMANAPRXNPADARXPPADATXPPADATXNPADARXNPADBRXPPADBTXPPADBTXNPADBNotes: 1. SM and ADC functionality in multi-function user I/O pins is reserved for future use.2. Dedicated SM and ADC pins are reserved for future use.UG075_06_050108Figure 3-19: FF1152 Flip-Chip Fine-Pitch BGA Pinout Diagram (FX100)Virtex-4 FPGA Packaging and Pinout Specification www.xilinx.com 261UG075 (v3.3) September 19, 2008

Chapter 3: Pinout DiagramsRFF1152 Color-Coded SelectIO and Bank InformationFF1152 - Top ViewABCDEFGHJKLMNPRTUVWYAAABACADAEAFAGAHAJAKALAMANAPA$ $ $ $ $ $ $ $ $ $ $ # # # # # # ' ' 'BC$ $ $ $ $ $ $ $ $ $ $ # # # # # # ' ' ' ' D$ $ $ $ $ $ $ $ $ $ # # # # # # # # ' ' ' E $ $ $ $ $ # # # # # # # # ' ' ' F $ $ $ $ $ $ # # # # # # # # ' ' ' G $ $ $ $ $ ! ! ! # # # # # ' ' ' ' ' H $ $ $ $ $ ! ! ! ! ! # # # # # # ' ' ' ' ' J $ $ $ $ $ $ ! ! ! ! ! # # # # # ' ' ' ' K $ $ ! ! ! # # # # # ' ' ' ' L $ $ $ # # ' ' ' ' ' ' M # # # ' ' ' ' ' N # # ' ' ' ' ' ' P ' ' ' ' ' ' R ' ' ' ' ' T ' ' U V W Y & & AA & & & AB & & % % AC & & & & & " " " % % AD & & & & & " " " " " % % % % % % AE & & & & & & " " " " " % % % % % AF & & & & & " " " % % % % % AG & & & & & & & & % % % % % % AH & & & & & & & & % % % % % AJ & & & & & & & & % % % % % % % % % % AK & & & & & & % % % % % % % % % % % % AL & & & & & & % % % % % % % % % % % AMANAP1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34ug075_06-color2_011905Figure 3-20: FF1152 Color-Coded SelectIO and Bank Information262 www.xilinx.com Virtex-4 FPGA Packaging and Pinout SpecificationUG075 (v3.3) September 19, 2008

RFF1513 Package Pinout Diagram (LX100, LX160, and LX200)FF1513 Package Pinout Diagram (LX100, LX160, and LX200)FF1513 (XC4VLX100, XC4VLX160, and XC4VLX200) - Top ViewABCDEFGHJKLMNPRTUVWYAAABACADAEAFAGAHAJAKALAMANAPARATAUAVAW1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39Z Z ZZ Z ZL JH YC PN B U D W 2 0 1M K AO IS S SS S S1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39ABCDEFGHJKLMNPRTUVWYAAABACADAEAFAGAHAJAKALAMANAPARATAUAVAWUser I/O PinsDedicated PinsOther PinsIO_LXXY_#Z ADC P PROG_BGNDMulti-Function Pins: C CCLKW PWRDWN_B R RSVDADC1 - ADC7 B CS_BU RDWR_BVBATTD0 - D31N D_INS SMVCCAUXCCD DONEK TCKVCCINTN_GCA DOUT_BUSY I TDIVCCOP_GCH HSWAPEN O TDOn NO CONNECTLCY INITM TMSSM1 - SM7 2 1 0 M2, M1, M0 J TDPVREFL TDNVRNVRPNotes: 1. SM and ADC functionality in multi-function user I/O pins is reserved for future use.2. Dedicated SM and ADC pins are reserved for future use.UG075_07_050108Figure 3-21: FF1513 Flip-Chip Fine-Pitch BGA Composite Pinout Diagram (LX100, LX160, and LX200)Virtex-4 FPGA Packaging and Pinout Specification www.xilinx.com 263UG075 (v3.3) September 19, 2008

Chapter 3: Pinout DiagramsRFF1513 Color-Coded SelectIO and Bank InformationFF1513 - Top View1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39ABCDEFGHJKLMNPRTUVWYAAABACADAEAFAGAHAJAKALAMANAPARATAUAVAW $ $ $ $ $ $ $ $ # # # # # # # # # $ $ $ $ $ $ $ $ # # # # # # # # # # $ $ $ $ $ $ $ $ # # # # # # # # ' ' ' $ $ $ $ $ $ $ $ # # # # # ' ' ' ' ' $ $ $ $ $ $ $ $ # # # # # # ' ' ' ' ' $ $ $ $ $ $ $ # # # # ' ' ' ' ' $ $ $ $ $ # # # # # # # ' ' ' '" " " $ $ $ $ # # # # ' ' ' ' ' '" " " $ $ $ $ ! ! ! # # # # # ' ' ' ' ' '" " " " $ $ ! ! # # ' ' ' ' ' ' '" " " " $ $ ! ! ! # # # ' ' ' ' ' '" " " " ! ! ! # ' ' ' ' ' ' '" " " " ! ! ' ' ' ' ' ! ! !" " " " " ! ! ! ' ' ' ! ! ! ! !" " " " " ' ' ! ! ! ! ! ! !" " " " " " " ! ! ! ! ! ! ! !" " " " " " " " ! ! ! ! ! ! ! ! ! !$ $ $ " " " " " " ! ! ! ! ! ! ! ! ! ! !$ $ $ " " " " " " ! ! # # ! ! ! ! ! !$ $ $ $ $ $ " " " # # # ! ! ! ! ! !$ $ $ $ $ $ " " $ $ # # # # # # ! ! !$ $ $ $ $ $ $ $ $ $ $ # # # # # # ! ! !$ $ $ $ $ $ $ $ $ $ # # # # # # # #$ $ $ $ $ $ $ $ # # # # # # #$ $ $ $ $ $ $ # # # # #$ $ $ $ $ " " " # # # # #$ $ $ " " # # # # & " " " # # # # & & & " " " % % # # # # & & " " % % # # # # & & & & & " " " % % % % # # # & & & & % % % % # # # & & & & & & & % % % % % & & & & % % % % % % % & & & & & & % % % % % % % % & & & & & % % % % % % % % & & & & & & & & % % % % % % % % & & & & & & & & & & % % % % % % % % & & & & & & & & & % % % % % % % % 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39ABCDEFGHJKLMNPRTUVWYAAABACADAEAFAGAHAJAKALAMANAPARATAUAVAWug075_07-color2_122104Figure 3-22: FF1513 Color-Coded SelectIO and Bank Information264 www.xilinx.com Virtex-4 FPGA Packaging and Pinout SpecificationUG075 (v3.3) September 19, 2008

EEEEEEEEEEEEEEEEEEEERFF1517 Package Pinout Diagram (FX100)FF1517 Package Pinout Diagram (FX100)FF1517 (XC4VFX100) - Top ViewABCDEFGHJKLMNPRTUVWYAAABACADAEAFAGAHAJAKALAMANAPARATAUAVAW1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39VVVVEE EEXXEVVVVVnn nn nn nn nn nn nn nn nn nn nnEVVVVET GX XEZ Z ZZ Z ZJH YC PN B U D W 2 0 1M K AO IS S SS S SG TX XEEEVVVVVE EVVVVVEVEEVVVXXEVVVn nn nn nn nn nn nn nn nn nn nn nnEVABCDEFGHJKLMNPRTUVWYAAABACADAEAFAGAHAJAKALAMANAPARATAUAVAWE V VVVEEVVEVVVLUser I/O PinsIO_LXXY_#Z ADCS SM GNDE AVCCAUXRXA RXNPADAC CCLKK TCK GNDAAVCCAUXRXB RXPPADAADC1 - ADC7B CS_BI TDI R RSVDAVCCAUXTX TXPPADAD0 - D31N D_INO TDO VBATTAVCCAUXMGT TXNPADACCD DONEM TMS VCCAUX V VTRXARXNPADBN_GCA DOUT_BUSY J TDP VCCINTVTTXARXPPADBP_GCH HSWAPEN L TDN VCCOVTRXBTXPPADBLCSM1 - SM7Y INITn NO CONNECT VTTXBTXNPADBVREF2 1 0 M2, M1, M0X MGTCLKVRNP PROG_BG MGTVREFVRPW PWRDWN_BT RTERMU RDWR_BNotes: 1. SM and ADC functionality in multi-function user I/O pins is reserved for future use.2. Dedicated SM and ADC pins are reserved for future use.Figure 3-23: FF1517 Flip-Chip Fine-Pitch BGA Composite Pinout Diagram (FX100)Multi-Function Pins:1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39Dedicated PinsVVVEOther PinsUG075_08b_050108Virtex-4 FPGA Packaging and Pinout Specification www.xilinx.com 265UG075 (v3.3) September 19, 2008

EEEEEEEEEEEEEEEEEEEEEEEEEChapter 3: Pinout DiagramsRFF1517 Package Pinout Diagram (FX140)FF1517 (XC4VFX140) - Top ViewABCDEFGHJKLMNPRTUVWYAAABACADAEAFAGAHAJAKALAMANAPARATAUAVAW1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39VVVVEE EEXXEVVVVVEVVVVEVVVVT GX XEZ Z ZZ Z ZJH YC PN B U D W 2 0 1M K AO IS S SS S SG TX XEEEVVVVVEVXXEVEVVVEE EVVVVVEEVVEVVVVVEEVABCDEFGHJKLMNPRTUVWYAAABACADAEAFAGAHAJAKALAMANAPARATAUAVAWE V VEEVVVVVLV1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39User I/O PinsDedicated PinsOther PinsIO_LXXY_#Multi-Function Pins:ADC1 - ADC7D0 - D31CCN_GCP_GCLCSM1 - SM7VREFVRNVRPZCBNADCCCLKCS_BD_INSKIOSMTCKTDITDORGNDGNDARSVDVBATTD DONEM TMS VCCAUX V VTRXARXNPADBA DOUT_BUSY Y INIT VCCINTVTTXARXPPADBH HSWAPEN J TDP VCCOVTRXBTXPPADB2 1 0 M2, M1, M0L TDN n NO CONNECT VTTXBTXNPADBP PROG_BX MGTCLKW PWRDWN_BG MGTVREFU RDWR_BT RTERMNotes: 1. SM and ADC functionality in multi-function user I/O pins is reserved for future use.2. Dedicated SM and ADC pins are reserved for future use.EVVVEAVCCAUXRXAAVCCAUXRXBAVCCAUXTXAVCCAUXMGTRXNPADARXPPADATXPPADATXNPADAUG075_08_050108Figure 3-24: FF1517 Flip-Chip Fine-Pitch BGA Composite Pinout Diagram (FX140)266 www.xilinx.com Virtex-4 FPGA Packaging and Pinout SpecificationUG075 (v3.3) September 19, 2008

RFF1517 Color-Coded SelectIO and Bank InformationFF1517 Color-Coded SelectIO and Bank InformationFF1517 - Top View1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39ABCDEFGHJKLMNPRTUVWYAAABACADAEAFAGAHAJAKALAMANAPARATAUAVAW6 6 6 6 6 6 6 6 6 6 1 1 5 5 5 5 5 5 5 5 5 9 96 6 6 6 6 6 6 6 6 6 6 1 5 5 5 5 5 5 5 5 9 9 9 96 6 6 6 6 6 6 6 6 6 6 1 1 1 1 5 5 5 5 5 5 5 5 9 9 96 6 6 6 6 6 6 6 6 6 6 6 3 3 3 1 1 5 5 5 5 5 5 5 5 9 9 910 10 10 10 6 6 6 6 6 1 1 1 3 3 1 1 1 5 5 5 5 5 5 5 5 9 9 910 10 10 10 6 6 6 6 6 6 1 1 3 3 3 1 1 1 5 5 5 5 5 9 9 9 9 910 10 10 6 6 6 6 6 1 1 3 3 3 1 1 5 5 5 5 5 9 9 9 9 910 10 10 10 10 6 6 6 1 1 1 3 3 1 1 5 5 5 5 5 9 9 9 13 1310 10 10 10 10 6 1 1 3 3 3 1 1 5 5 5 5 5 9 9 9 1310 10 10 10 10 10 1 1 1 1 1 1 5 5 5 9 9 9 9 13 1310 10 10 10 10 10 10 10 1 1 1 1 1 1 9 9 9 9 9 1310 10 10 10 10 10 10 10 1 1 9 9 9 13 13 1310 10 10 10 10 10 10 1 9 9 9 13 13 1310 10 10 10 10 10 10 10 10 9 9 9 9 13 13 1314 14 14 10 10 10 10 14 14 9 9 9 9 9 9 9 13 13 1314 14 14 14 10 14 14 14 14 14 9 9 9 9 9 13 13 13 1314 14 14 14 14 14 14 14 14 14 14 14 9 9 13 13 13 13 13 13 1314 14 14 14 14 14 14 14 14 14 13 13 13 13 13 13 13 13 1314 14 14 14 14 14 14 12 12 13 13 13 13 13 13 13 13 13 13 13 1314 14 14 12 12 12 12 12 13 13 13 13 13 11 13 13 13 1314 14 14 12 12 12 12 12 12 12 13 13 11 11 11 11 13 13 1314 14 14 12 12 12 12 11 11 11 11 11 11 11 11 1114 14 14 12 12 2 11 11 11 11 11 11 1114 14 14 12 12 12 2 2 11 11 11 11 11 11 11 1114 12 12 12 12 12 2 2 2 2 2 2 11 11 11 11 11 11 11 1114 14 12 12 12 12 12 8 8 8 2 2 2 2 2 2 11 11 11 11 11 1114 12 12 12 8 8 8 8 8 2 2 4 4 4 2 2 7 11 11 11 11 1114 14 12 12 12 8 8 8 8 8 2 2 4 4 2 2 7 7 7 11 11 11 11 1112 12 12 12 12 8 8 8 8 8 2 2 4 4 4 2 2 7 7 7 7 7 11 11 1112 12 12 12 12 8 8 8 8 2 2 2 4 4 4 2 2 7 7 7 7 7 7 11 11 11 1112 12 12 8 8 8 8 8 8 8 8 2 2 2 4 4 2 2 2 7 7 7 7 7 11 11 11 1112 12 12 8 8 8 8 8 8 8 8 2 2 4 4 4 7 7 7 7 7 7 7 7 7 7 7 712 12 12 8 8 8 8 8 8 8 8 2 2 2 2 2 2 7 7 7 7 7 7 7 7 7 7 712 12 12 12 8 8 8 8 8 8 8 8 8 2 7 7 7 7 7 7 7 7 7 7 712 12 8 8 8 8 8 8 8 8 8 2 7 7 7 7 7 7 7 7 7 71 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39ABCDEFGHJKLMNPRTUVWYAAABACADAEAFAGAHAJAKALAMANAPARATAUAVAWFigure 3-25: FF1517 Color-Coded SelectIO and Bank Informationug075_08-color2_01107Virtex-4 FPGA Packaging and Pinout Specification www.xilinx.com 267UG075 (v3.3) September 19, 2008

Chapter 3: Pinout DiagramsR268 www.xilinx.com Virtex-4 FPGA Packaging and Pinout SpecificationUG075 (v3.3) September 19, 2008

RChapter 4Mechanical DrawingsSummaryThis chapter provides mechanical drawings of the following Virtex-4 FPGA packages:• “SF363 Flip-Chip Fine-Pitch BGA Package Specifications (0.80 mm pitch),” page 270• “FF668 Flip-Chip Fine-Pitch BGA Package Specifications (1.00 mm pitch),” page 271• “FF672 Flip-Chip Fine-Pitch BGA Package Specifications (1.00 mm pitch),” page 272• “FF676 Flip-Chip Fine-Pitch BGA Package Specifications (1.00 mm pitch),” page 273• “FF1148 Flip-Chip Fine-Pitch BGA Package Specifications (1.00 mm pitch),” page 274• “FF1152 Flip-Chip Fine-Pitch BGA Package Specifications (1.00 mm pitch),” page 275• “FF1513 Flip-Chip Fine-Pitch BGA Package Specifications (1.00 mm pitch),” page 276• “FF1517 Flip-Chip Fine-Pitch BGA Package Specifications (1.00 mm pitch),” page 277Virtex-4 FPGA Packaging and Pinout Specification www.xilinx.com 269UG075 (v3.3) September 19, 2008

Chapter 4: Mechanical DrawingsRSF363 Flip-Chip Fine-Pitch BGA Package Specifications (0.80 mm pitch)Figure 4-1: SF363 Flip-Chip Fine-Pitch BGA Package SpecificationsUG075_c4_01_052208270 www.xilinx.com Virtex-4 FPGA Packaging and Pinout SpecificationUG075 (v3.3) September 19, 2008

RSummaryFF668 Flip-Chip Fine-Pitch BGA Package Specifications (1.00 mm pitch)Figure 4-2: FF668 Flip-Chip Fine-Pitch BGA Package SpecificationsVirtex-4 FPGA Packaging and Pinout Specification www.xilinx.com 271UG075 (v3.3) September 19, 2008

Chapter 4: Mechanical DrawingsRFF672 Flip-Chip Fine-Pitch BGA Package Specifications (1.00 mm pitch)Figure 4-3: FF672 Flip-Chip Fine-Pitch BGA Package Specifications272 www.xilinx.com Virtex-4 FPGA Packaging and Pinout SpecificationUG075 (v3.3) September 19, 2008

RSummaryFF676 Flip-Chip Fine-Pitch BGA Package Specifications (1.00 mm pitch)Figure 4-4: FF676 Flip-Chip Fine-Pitch BGA Package SpecificationsVirtex-4 FPGA Packaging and Pinout Specification www.xilinx.com 273UG075 (v3.3) September 19, 2008

Chapter 4: Mechanical DrawingsRFF1148 Flip-Chip Fine-Pitch BGA Package Specifications (1.00 mm pitch)Figure 4-5: FF1148 Flip-Chip Fine-Pitch BGA Package Specifications274 www.xilinx.com Virtex-4 FPGA Packaging and Pinout SpecificationUG075 (v3.3) September 19, 2008

RSummaryFF1152 Flip-Chip Fine-Pitch BGA Package Specifications (1.00 mm pitch)Figure 4-6: FF1152 Flip-Chip Fine-Pitch BGA Package SpecificationsVirtex-4 FPGA Packaging and Pinout Specification www.xilinx.com 275UG075 (v3.3) September 19, 2008

Chapter 4: Mechanical DrawingsRFF1513 Flip-Chip Fine-Pitch BGA Package Specifications (1.00 mm pitch)Figure 4-7: FF1513 Flip-Chip Fine-Pitch BGA Package Specifications276 www.xilinx.com Virtex-4 FPGA Packaging and Pinout SpecificationUG075 (v3.3) September 19, 2008

RSummaryFF1517 Flip-Chip Fine-Pitch BGA Package Specifications (1.00 mm pitch)Figure 4-8: FF1517 Flip-Chip Fine-Pitch BGA Package SpecificationsVirtex-4 FPGA Packaging and Pinout Specification www.xilinx.com 277UG075 (v3.3) September 19, 2008

Chapter 4: Mechanical DrawingsR278 www.xilinx.com Virtex-4 FPGA Packaging and Pinout SpecificationUG075 (v3.3) September 19, 2008

RChapter 5Thermal SpecificationsSummaryIntroductionThis chapter provides thermal data associated with Virtex-4 FPGA packages. Thefollowing topics are discussed:• Introduction• Virtex-4 FPGA Power Management Strategy• Some Thermal Management Options• Support for Compact Thermal Models (CTM)• ReferencesVirtex-4 devices are offered exclusively in thermally efficient flip-chip BGA packages. ThisFPGA family’s three product lines have different thermal needs. The LX devices are thebase family members, with traditional Virtex-II FPGA features implemented in the smallerprocess technology. The FX and SX family members take system integration a few stepsfurther, with the incorporation of embedded circuits on top of the base FPGA fabric.Similar to Virtex-II FPGAs, all Virtex-4 family members feature versatile SelectIO resourcesthat support a variety of I/O standards, on-board digitally controlled impedance (DCI),and many other popular features contained in earlier Virtex FPGA products. In addition,the FX family incorporates faster RocketIO multi-gigabit transceivers (MGTs) and one ormore embedded PowerPC devices. The SX devices include an embedded DSP. The extentof system integration in a fully configured design that is exploiting the fabric and usingseveral embedded circuits and systems (such as PowerPC devices, MGTs, SelectIO buseswith DCI, and so forth) presents a power consumption challenge that must be managed.Unlike features in an ASIC or a microprocessor, the combination of FPGA features utilizedin an end-user application will not be known to the component supplier. Therefore, itremains a challenge for Xilinx to predict the power requirements of a given Virtex-4 devicewhen it leaves the factory. Accurate estimates are obtained when the board design takesshape. For this purpose, Xilinx offers and supports a suite of integrated device poweranalysis tools to help end-users quickly and accurately estimate their design powerrequirements. The uncertainty of design power requirements makes it difficult to applycanned thermal solutions to fit all users. Therefore, Xilinx ® devices do not come withpreset thermal solutions. The end user’s operating conditions dictate the appropriatesolution.The Virtex-4 FPGA package offering (see Table 5-1) is tailored to include medium to highpoweroptions that allow external management of power to suit the user application.Table 5-1 also shows the thermal resistance data for Virtex-4 devices in the packagesVirtex-4 FPGA Packaging and Pinout Specification www.xilinx.com 279UG075 (v3.3) September 19, 2008

Chapter 5: Thermal SpecificationsRoffered. The data includes junction-to-ambient in still air and at various air speeds (inLFM), junction-to-case and junction-to-board data based on standard JEDEC four-layermeasurements. Compact thermal models for these products are available on the Xilinxsupport download center at: http://www.xilinx.com/support/download/index.htm.Table 5-1: Thermal Resistance DataPackage Device Package Body Size θ JC θ JBθ JA @0 LFMLX and SX Devicesθ JA @250 LFMθ JA @500 LFMθ JA @750 LFMSF363 LX15 17.0 0.5 5.6 20.8 14.7 12.9 12.0LX25 17.0 0.3 4.9 19.0 13.5 11.8 11.0FF668 LX15 27.0 0.6 4.4 14.2 9.3 7.8 7.1LX25 27.0 0.4 4.0 13.4 8.7 7.3 6.7LX40 27.0 0.3 3.6 13.0 8.5 7.1 6.5LX60 27.0 0.2 3.4 12.4 8.1 6.8 6.2SX25 27.0 0.4 3.9 13.4 8.7 7.3 6.7SX35 27.0 0.2 3.6 12.7 8.3 7.0 6.4FF676 LX15 27.0 0.6 4.4 14.2 9.3 7.8 7.1LX25 27.0 0.4 4.0 13.4 8.7 7.3 6.7FF1148 LX40 35.0 0.3 2.8 11.0 6.7 5.5 4.9LX60 35.0 0.2 2.6 10.6 6.4 5.3 4.8LX80 35.0 0.2 2.4 10.4 6.3 5.1 4.6LX100 35.0 0.1 2.2 10.1 6.1 5.0 4.5LX160 35.0 0.1 2.1 9.7 5.9 4.8 4.3SX55 35.0 0.2 2.4 10.3 6.3 5.1 4.6FF1513 LX100 40.0 0.1 2.3 9.7 5.8 4.7 4.2FX DevicesLX160 40.0 0.1 2.2 9.3 5.6 4.5 4.0LX200 40.0 0.1 2.0 9.1 5.5 4.4 4.0SF363 FX12 17.0 0.5 5.7 20.8 14.7 12.9 12.0FF668 FX12 27.0 0.6 4.4 14.2 9.3 7.8 7.1FF672 FX20 27.0 0.4 3.8 13.5 8.7 7.4 6.8FX40 27.0 0.2 3.3 12.6 8.2 6.9 6.3FX60 27.0 0.1 3.1 12.0 7.7 6.5 5.9FF1152 FX40 35.0 0.2 2.6 10.7 6.5 5.3 4.8FX60 35.0 0.2 2.5 10.2 6.2 5.1 4.7FX100 35.0 0.1 2.2 9.9 6.0 4.9 4.4FF1517 FX100 40.0 0.1 2.2 9.5 5.7 4.6 4.1FX140 40.0 0.1 2.0 8.6 5.0 4.1 3.7280 www.xilinx.com Virtex-4 FPGA Packaging and Pinout SpecificationUG075 (v3.3) September 19, 2008

RVirtex-4 FPGA Power Management StrategyVirtex-4 FPGA Power Management StrategyXilinx relies on a multi-prong approach with regards to the heat-dissipating potential ofVirtex-4 devices:• Design and SiliconSignificant power reduction in Virtex-4 devices at the 90 nm node is achieved throughinnovative process and circuit design. Transistor leakage current is minimized (50%better than comparable devices) by using the power-efficient Virtex-4 FPGAarchitecture. Despite these improvements, and a lower operating voltage, the Virtex-4devices pack higher gate density and can do more in a shorter time than the previousgeneration of FPGAs. Compared to previous generations, the power consumption islower for the same design (same function and gate density) in a Virtex-4 FPGAimplementation.However, with the increase in resources associated with higher gate density devices,switching at faster rates, Xilinx anticipates more work will be done more quickly, thusdissipating more power than before.• PackagingAt the package component level, Xilinx has selected the more efficient flip-chip BGApackages, which present a low thermal path to the outside. This package incorporatesa heat spreader with a thermal interface material (TIM), as shown in Figure 5-1.Thermal Interface Material (TIM)Lid-Heat SpreaderDieSubstrateUG075_c05_01_081905Figure 5-1: Heat Spreader with Thermal Interface MaterialMaterials with better thermal conductivity and consistent process applications deliverlow thermal resistance up to the heat spreader. The junction-to-case thermal resistance(top of heat spreader) of all Virtex-4 FPGA packages is less than 0.5•C/watt. Typicallythis value is between 0.1 to 0.3 •C/watt for the larger packages (35 mm x 35 mm andabove).Virtex-4 FPGA Packaging and Pinout Specification www.xilinx.com 281UG075 (v3.3) September 19, 2008

Chapter 5: Thermal SpecificationsR• Heat Sinking Solutions at the System LevelDepending on the system’s physical as well as mechanical constraints, the expectationis that the thermal budget will be maintained with custom or OEM heat sink solutions,providing the third prong in the thermal management strategy. At this point, Xilinxhas left the heat sink solution to the system level designers who can tailor the designand solution to the constraints of their systems, being fully aware that the part hascertain inherent capabilities for delivering the heat to the surface.The Virtex-4 FPGA packages can be grouped into medium- and high-performancepackages based on their power handling capabilities. All Virtex-4 FPGA packages canuse thermal enhancements, ranging from simple airflow to schemes that can includepassive as well as active heat sinks. This is particularly true for the bigger flip-chipBGA packages where system designers have the option to further enhance thepackages with bigger and more elaborate heat sinks to handle excesses of 20 wattswith arrangements that consider system physical constraints.Some Thermal Management OptionsThe flip-chip thermal management chart in Figure 5-2 illustrates simple but incrementalpower management schemes that can be applied on a flip-chip BGA package.Low End1 - 6 WattsBare Package withModerate Air8 - 12° C/WattBare PackagePackage can beused with moderateairflow within a systemMid Range4 - 10 WattsPassive H/S + Air5 - 10° C/WattPackaged Used withVarious Forms ofPassive Heat SinksHeat spreader techniquesHigh End8 - 25 WattsActive Heat Sink2 - 3° C/Wattor BetterPackage Used withActive Heat SinksTEC and board levelheat spreader techniquesUG075_c5_02_091205Figure 5-2: Thermal Management Options for Flip-Chip BGA Packages• For moderate power dissipation (less than 6 watts), the use of passive heat sinks andheat spreaders attached with thermally conductive double-sided tapes or retainers(with TIM around 0.2•C/watt) can offer quick thermal solutions in these packages.• The use of lightweight, finned, external, passive heat sinks can be effective fordissipating up to 10 - 20 watts in the bigger packages. The more efficient external heatsinks tend to be tall and heavy. To help protect component joints from heat sinkinduced stress cracks, the use of spring-loaded pins or clips that transfer the mountingstress to a circuit board is advisable whenever a bulky heat sink is considered. Thediagonals of some of these heat sinks may be designed with extensions to allow directconnection to the board.• As stated earlier, the flip-chip BGA packages offered for Virtex-4 devices are thermallyenhanced BGAs with the die facing down. These packages have an exposed metalheat sink at the top. These high-end thermal packages lend themselves to theapplication of efficient external heat sinks (passive or active) for further heat removalefficiency. Again, precautions must be taken to prevent component damage when a282 www.xilinx.com Virtex-4 FPGA Packaging and Pinout SpecificationUG075 (v3.3) September 19, 2008

RSupport for Compact Thermal Models (CTM)bulky heat sink is attached. The thermal interface resistance needs to be controlled totake full advantage of these packages.• An active heat sink may include a simple heat sink incorporating a mini fan or even aPeltier Thermoelectric Cooler (TEC) with a fan to carry away any dissipated heat.When considering the use of a TEC for heat management, consultation with experts inusing the device is important because these devices can be reversed and causedamage to components. Also condensation can be an issue with these devices.• Outside the package itself, the board on which the package sits can have a significantimpact on thermal performance. As much as 60 to 80% of the dissipated heat can gothrough the BGA balls and thus to the board. Using the standard four-layer JEDECboards, these with their multiple internal vias show very efficient junction-to-boardresistances. Designs can be implemented to take advantage of the board's ability tospread heat. The effect of the board is dependent on its size and how it conducts heat.Board size, the level of copper traces on it, the number of buried copper planes alllower the junction-to-ambient thermal resistance for a package mounted on it. Thecold ring junction-to-board thermal resistance for Virtex-4 FPGA packages are givenin Table 5-1. Users need to be aware that a direct heat path to the board from acomponent also exposes the component to the effect of other heat sources on theboard, particularly if the board is not cooled effectively. An otherwise coolercomponent can be heated by other heat contributing components on the board.Table 5-1 lists the junction-to-board thermal parameters for Virtex-4 FPGA packages.A standard JEDEC type board in still air was used for the data estimation. Users needto be aware that a direct heat path to the board from a component also exposes thecomponent to the effect of other heat sources, particularly if the board is not cooledeffectively. An otherwise cooler component can be heated by other heat contributingcomponents on the board.Support for Compact Thermal Models (CTM)Table 5-1 provides the traditional thermal resistance data for Virtex-4 devices. Theseresistances are measured using a prescribed JEDEC standard that may not necessarilyreflect the actual user environment. The quoted θ JA , and θ JC numbers are environmentallydependent, and JEDEC has traditionally recommended that these be used with thatawareness. For more accurate junction temperature prediction, these may not be enough,and a system level thermal simulation may be required. Though Xilinx will continue tosupport these figure of merit data, for Virtex-4 FPGA boundary condition independentcompact thermal models (BCI-CTM) are available to assist end-users in their thermalsimulations.Two resistor as well as eight to 10 resistor network models are offered for all Virtex-4devices. These compact models seek to capture the thermal behavior of the packages moreaccurately at pre-determined critical points (junction, case, top, leads, etc.) with thereduced set of nodes as illustrated in Figure 5-3.Unlike a full 3D model, these are computationally efficient and work well in an integratedsystem simulation environment. The two-resistor model can be made up with the dataprovided in Table 5-1. Delphi CTM models are available on the Xilinx support downloadcenter at: http://www.xilinx.com/support/download/index.htm.Virtex-4 FPGA Packaging and Pinout Specification www.xilinx.com 283UG075 (v3.3) September 19, 2008

Chapter 5: Thermal SpecificationsRDELPHI BCI-CTM Topology forFCBGATITOTwo Resistor ModelR jcJunctionSIDEJunctionR jbBIBOUG075_c05_02_081905Figure 5-3: Thermal Model TopologiesReferencesThe following websites contain additional information on heat management and contactinformation:• http://www.wakefield.com• http://www.aavidthermalloy.com• http://www.qats.comRefer to the following websites for interface material sources:• Power Devices - http://www.powerdevices.com• Bergquist Company - http://www.bergquistcompany.com• AOS Thermal Compound - http://www.aosco.com• Chomerics - http://www.chomerics.com• Kester - http://www.kester.comRefer to the following websites for CFD tools that Xilinx supports with thermal models.• Flomerics - Flotherm and FloPCB - http://www.flotherm.com• ANSYS - Icepak - http://www.ansys.com/products/icepak284 www.xilinx.com Virtex-4 FPGA Packaging and Pinout SpecificationUG075 (v3.3) September 19, 2008

RChapter 6Package MarkingVirtex-4 Device Package MarkingAll Virtex-4 devices have package markings similar to the example shown in Figure 6-1and explained in Table 6-1.®Device TypePackageLot CodeSpeed GradeVirtex-4XC4VLX25 FF668 xxx XXXXxxxxxxxxxX10CCircuit Design RevisionCxx: Designates a Step 1 DeviceDxx: Designates a Step 2 DeviceDate CodeStepping Identification(Step 0 is not always marked)Operating Rangeug075_ch06_01_020906Figure 6-1: Virtex-4 Device Package MarkingTable 6-1: Xilinx Device Marking Definition—ExampleItemXilinx LogoFamily BrandLogo1st Line2nd Line3rd Line (1, 2) TenDefinitionXilinx logo, Xilinx name with trademark, and trademark-registered status.Family name with trademark and trademark-registered status (Virtex-4). This line is optional andcould appear blank.Device namePackage type and pin count, circuit design revision, the location code for the wafer fab, thegeometry code, and date code.A G in the third letter of a package type indicates a Pb-free RoHS compliant package. For moredetails on Xilinx Pb-Free and RoHS Compliant Products, see:http://www.xilinx.com/system_resources/lead_free/index.htm.alphanumeric characters for Assembly, Lot, and Step information. The last digit is usually anA or an M if a stepping version does not exist. In this example, the last number on this lineindicates the stepping version of the device (2).Virtex-4 FPGA Packaging and Pinout Specification www.xilinx.com 285UG075 (v3.3) September 19, 2008

Chapter 6: Package MarkingRTable 6-1: Xilinx Device Marking Definition—Example (Continued)ItemDefinitionDevice speed grade and temperature range. If a grade is not marked on the package, the productis considered commercial grade.Other variations for the 4th line:4th Line10C xxxx10CES10CESn10CESnLor10CESnRThe xxxx indicates the SCD for the device. An SCD is a special ordering code that isnot always marked in the device top mark.The ES indicates an Engineering Sample.The n is a numeral (n = 1, 2, 3…).The ESn indicates an Engineering Sample n, for example, ES1, ES2, ES3, and so on.This device marking is only used for Virtex-4 FX engineering sample devices. The Lindicates that only left MGTs are available and the R indicates that only the rightMGTs are available when looking at the device from the bottom-side up.Notes:1. Some Virtex-4 LX and SX Step 1 devices do not have the 1 marked on the package top mark.2. FX Step 0 devices do not have the 0 marked on the package top mark.286 www.xilinx.com Virtex-4 FPGA Packaging and Pinout SpecificationUG075 (v3.3) September 19, 2008